Cross-platform CLI and Python drivers for AIO liquid coolers and other devices

**No Longer Maintained** Official RAMCloud repo

Ramulator 2.0 is a modern, modular, extensible, and fast cycle-accurate DRAM simulator. It provides support for agile implementation and evaluation of new memory system designs (e.g., new DRAM standards, emerging RowHammer mitigation techniques). Described in our paper https://people.inf.ethz.ch/omutlu/pub/Ramulator2_arxiv23.pdf

DRAMSim2: A cycle accurate DRAM simulator

DRAM Bender is the first open source DRAM testing infrastructure that can be used to easily and comprehensively test state-of-the-art HBM2 chips and DDR4 modules of different form factors. Six prototypes are available on different FPGA boards. Described in our preprint: https://arxiv.org/pdf/2211.05838.pdf

MCMC toolbox for Matlab

Generic FPGA SDRAM controller, originally made for AS4C4M16SA

Persist and reuse KV Cache to speedup your LLM.

Artifacts for "Phoenix: Rowhammer Attacks on DDR5 with Self-Correcting Synchronization" (IEEE S&P '26)

A 1MB chip RAM expansion for the A500+

A High-Level DRAM Timing, Power and Area Exploration Tool

Sample Arduino program to test 4164 DRAM chips.

FlippyRAM is an automated framework for testing and analyzing Rowhammer vulnerabilities in DRAM. It combines rowhammer tools and supports both Docker and ISO-based execution, making it a powerful resource for hardware security research.

BEER determines an ECC code's parity-check matrix based on the uncorrectable errors it can cause. BEER targets Hamming codes that are used for DRAM on-die ECC but can be extended to apply to other linear block codes (e.g., BCH, Reed-Solomon). BEER is described in the 2020 MICRO paper by Patel et al.: https://arxiv.org/abs/2009.07985.

A PIM instrumentation, compilation, execution, simulation, and evaluation repository for BLIMP-style architectures.

Circuit-level model for the Capacity-Latency Reconfigurable DRAM (CLR-DRAM) architecture. This repository contains the SPICE models of the CLR-DRAM architecture and the baseline architecture used in our ISCA 2020 paper "Luo et al., CLR-DRAM: A Low-Cost DRAM Architecture Enabling Dynamic Capacity-Latency Trade-Off": https://people.inf.ethz.ch/omu…

An RTL-level, Chipyard-compatible DRAM simulator model for high fidelity memory simulations.

A survey of manufacturer-provided DRAM operating parameters and timings as specified by DRAM chip datasheets from between 1970 and 2021. This data and its analysis are described in the 2022 paper by Patel et al.: https://arxiv.org/abs/2204.10378

Implementation of flush + reload attack to extract private key from the GnuPG implementation of RSA.

Bayesian Inference. Parallel implementations of DREAM, DE-MC and DRAM.