CPUNexus
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VeriGPU
VeriGPU PublicForked from hughperkins/VeriGPU
OpenSource GPU, in Verilog, loosely based on RISC-V ISA
SystemVerilog 1
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tiny-gpu
tiny-gpu PublicForked from adam-maj/tiny-gpu
A minimal GPU design in Verilog to learn how GPUs work from the ground up
SystemVerilog 1
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fpu
fpu PublicForked from dawsonjon/fpu
synthesiseable ieee 754 floating point library in verilog
Verilog 1
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ccpu
ccpu PublicForked from imihajlow/ccpu
A 8-bit computer made of 74xx series logic gates and memory ICs.
Assembly
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PASC
PASC PublicForked from jbush001/PASC
Parallel Array of Simple Cores. Multicore processor.
Verilog
Repositories
- microwatt Public Forked from antonblanchard/microwatt
A tiny Open POWER ISA softcore written in VHDL 2008
CPUNexus/microwatt’s past year of commit activity - Tridora-CPU-mirror Public
CPUNexus/Tridora-CPU-mirror’s past year of commit activity - darkriscv Public Forked from darklife/darkriscv
opensouce RISC-V cpu core implemented in Verilog from scratch in one night!
CPUNexus/darkriscv’s past year of commit activity - tiny-gpu Public Forked from adam-maj/tiny-gpu
A minimal GPU design in Verilog to learn how GPUs work from the ground up
CPUNexus/tiny-gpu’s past year of commit activity - cva6 Public Forked from openhwgroup/cva6
The CORE-V CVA6 is an Application class 6-stage RISC-V CPU capable of booting Linux
CPUNexus/cva6’s past year of commit activity - neorv32-verilog Public template Forked from stnolting/neorv32-verilog
♻️ Convert the NEORV32 processor into a synthesizable plain-Verilog netlist module using GHDL.
CPUNexus/neorv32-verilog’s past year of commit activity - neorv32 Public Forked from stnolting/neorv32
🖥️ A tiny, customizable and extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independent VHDL.
CPUNexus/neorv32’s past year of commit activity
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