724results about "Delta modulation" patented technology

A variable capacitance switched capacitor input system and method includes a differential integrator circuit having first and second input summing nodes and a variable sensing capacitor; one terminal of the variable sensing capacitor is connected to one of the nodes in the first phase and to the other of the nodes in the second phase; an input terminal connected to a second terminal of the variable sensing capacitor receives a first voltage level in the first phase and a second voltage level in the second phase for delivering the charge on the variable sensing capacitor to the first summing node in the first phase and to the second summing node in the second phase and canceling errors in a differential integrator circuit output caused by leakage current.

A method and apparatus for providing a substantially real-time representation of an analog representation of a physiological signal. The waveform signal from the sensor is converted into digital form. A delta-sigma modulator is used as a simple Digital-to-analog Converter (ADC). The output can then be provided through a simple hardware filter to give an analog output signal in nearly real-time, which can be used for other instruments, synchronization, display, etc.

Sample rate converters are known, and are used to convert a signal with a first sample rate (sampling frequency) into a signal with a second sample rate (sampling frequency). To obtain a flexible sample rate converter with sampling frequencies that are not known beforehand, until now only sample rate converters with very high intermediate sampling frequencies are known. The invention provides a flexible sample rate converter, which is able to handle unknown input and output sampling frequencies. This is achieved by using polyphase decomposition filter means in combination with interpolation means.

A low power delta-sigma analog to digital converter 10 for converting current mode signals without an amplifier includes an integration capacitor 26, a comparator 30, and a first switch 24 in parallel with one another and coupled to an integration node 28. A FET 20 and the first switch are disposed in series between a dump capacitor 25 and the integration node. A second switch 27 operates to discharge the dump capacitor, and an output of the comparator controls both switches in opposition. Preferably, no op-amps are included in the circuit, and current is supplied by an imaging component 5. In a first comparator state, the first capacitor charges, the first switch is open and the second switch is closed, and the dump capacitor discharges. In a comparator second state, the first switch is closed and the second switch is open, and the integration capacitor transfers a fixed amount of charge into the dump capacitor through an injection FET operating in saturation.

A control mechanism that can be used to control a SIGMADELTA ADC to provide the required level of performance while reducing power consumption. The SIGMADELTA ADC is designed with multiple stages (i.e., loops or sections), and provides improved performance (e.g., higher dynamic range) as more stages are enabled. The control mechanism selectively enables a sufficient number of stages to provide the required performance and disables remaining stages to conserve power. The control mechanism achieves this by measuring one or more characteristics (e.g., signal level) of the ADC input signal through a SIGMADELTA ADC that is similar to the SIGMADELTA ADC on the signal path, comparing the measured characteristic(s) to particular threshold level(s), and controlling the stages such that the desired objectives are achieved. In one implementation, the control circuit includes one or more detector stages, a conditioning circuit, and a signal processor. The detector stage(s) receive the input signal and provide a detected signal. The conditioning circuit receives the detected signal and provides conditioned samples. The signal processor receives the conditioned samples and provides a control signal that selectively disables zero or more SIGMADELTA stages in the SIGMADELTA ADC.

A switched capacitor circuit includes an amplifier, a charging unit, an offset unit, and an integrating unit. The charging unit is coupled between an input node and a first node, and is for accumulating charge corresponding to an input signal during a sampling mode. The offset unit is coupled between the first node and an input of the amplifier, and is for maintaining the first node to be a virtual ground during an integrating mode. The integrating unit is coupled between the first node and an output of the amplifier, and is for receiving charge from the charging unit during the integrating mode.

Systems and methods are discussed for using a floating-gate MOSFET as a programmable reference circuit. One example of the programmable reference circuit is a programmable voltage reference source, while a second example of a programmable reference circuit is a programmable reference current source. The programmable voltage reference source and / or the reference current source may be incorporated into several types of circuits, such as comparator circuits, current-mirror circuits, and converter circuits. Comparator circuits and current-mirror circuits are often incorporated into circuits such as converter circuits. Converter circuits include analog-to-digital converters and digital-to-analog converters.

A signal processing system includes a jointly non-linear delta sigma modulator. In one embodiment, the jointly non-linear delta sigma modulator includes a non-linear quantization transfer function, and the output of the delta sigma modulator is defined, at least in part, by a non-linear interrelationship of multiple noise-shaping filter state variables. A look-ahead delta-sigma modulator can be implemented as a noise shaping filter and a function generator. State variables of the noise shaping filter provide the input data from which the function generator determines a quantizer output signal. Latter state variables are more dominant in determining the quantizer output signal. Accordingly, earlier state variables can be approximated to a greater degree than latter state variables without significant compromise in quantization accuracy.

A high-performance delta sigma analog-to-digital converter. The high-performance delta sigma analog-to-digital converter includes a first mechanism for converting an input analog signal to a digital output signal. The first mechanism is characterized by a transfer function that is altered relative to an ideal transfer function. A second mechanism compensates for the alteration in the transfer function via a single additional digital-to-analog converter. In a specific embodiment, the alteration includes an additional pole and an additional zero induced by feedback delays in the first mechanism. The feedback delays include signal dependent jitter delay and feedback digital-to-analog converter cell switching delays. The second mechanism includes an additional latch that compensates for the signal dependent jitter delay. The first mechanism includes a resonator and a quantizer. The second mechanism includes a feedback path from an output of the quantizer to the resonator. The feedback path includes a first latch positioned between an output of the quantizer and the additional digital-to-analog converter. The additional latch is positioned at an output of the first latch and eliminates signal dependent jitter delay in the analog-to-digital converter. The additional feedback digital-to-analog converter is a non-return-to-zero digital-to-analog converter, an output of which is connected to the resonator.

Each of plural sigma-delta modulators having a sampling capacitor, an integrator, and a quantizer are connected to each other in parallel. Each of the sigma-delta modulators conducts parallel oversampling in which an analog input signal is sampled by a sampling capacitor, and the sampling result is quantized by the integrator and the quantizer. Then, the quantized values of the sigma-delta modulators are added to obtain MSBs, the residue values of the integrators after quantizing in the respective sigma-delta modulators are added, and the addition result of the residue values is converted analog-to-digital to obtain LSBs.

A bandpass SIGMADELTA ADC utilizing either a single-loop or a MASH architecture wherein the resonators are implemented as either a delay cell resonator, a delay cell based resonator, a Forward-Euler resonator, a two-path interleaved resonator, or a four-path interleaved resonator. The resonator can be synthesized with analog circuit techniques such as active-RC, gm-C, MOSFET-C, switched capacitor, or switched current. The switched capacitor or switched current circuits can be designed using single-sampling, double-sampling, or multi-sampling circuits. The non-stringent requirement of a SIGMADELTA ADC using switched capacitor circuits allows the ADC to be implemented in a CMOS process to minimize cost and reduce power consumption. Double-sampling circuits provide improved matching and improved tolerance to sampling clock jitter. In particular, a bandpass MASH 4-4 SIGMADELTA ADC provides a simulated signal-to-noise ratio of 85 dB at an oversampling ratio of 32 for a CDMA application. The bandpass SIGMADELTA ADC can also be used in conjunction with undersampling to provide a frequency downconversion.

A method of controlling a sigma delta modulator with a loop which establishes a signal transfer function, STF, and a quantization noise transfer function, NTF, of the sigma delta modulator, wherein the sigma delta modulator receives an input signal, x(n), and provides a modulated output signal, y(n) in response to the input signal. The method is characterized in comprising the step of controlling the sigma delta modulator to change the quantization noise transfer function, NTF, in response to a signal feature, A(n), which is correlated with the input signal.

A time difference adder included in a system-on-chip (SOC) includes a first register unit and a second register unit. The first register unit is configured to receive first and second input signals having a first time difference, and generate a first output signal in response to a first signal. The second register unit is configured to receive third and fourth input signals having a second time difference, and generate a second output signal having a third time difference with respect to the first output signal in response to the first signal. The third time difference corresponds to a sum of the first time difference and the second time difference.

A signal processing system includes an analog-to-digital delta sigma modulator with a duty cycle modulator and a finite impulse response (FIR) filter in a main loop feedback path of the delta sigma modulator. The duty cycle modulator and FIR filter can provide high performance filtering in the main loop feedback path. To prevent instability in the main loop caused by the duty cycle modulator and FIR filter, the delta sigma modulator also includes a stabilizer loop. Transfer functions of the main loop and the stabilizer loop combine to achieve a target transfer function for the analog-to-digital delta sigma modulator that provides for stable operation of the analog-to-digital delta sigma modulator. In at least one embodiment, the stabilizer loop includes a stabilizer path that provides output data directly to an integrator of the main loop filter.

Signal conversion is implemented employing a memory system operating as a look-up table that stores a plurality of sets of output samples associated with each of a plurality of respective input samples. The look-up table thus can generate a corresponding set of output samples in response to a given input sample, thereby emulating desired digital upsampling and delta-sigma modulation. The output samples can be aggregated, such as by multiplexing, to provide an output data stream at a desired sample rate.

A fourth order delta sigma analog-to-digital converter is presented, comprising a passive delta sigma modulator including a passive filter, a quantizer, and a digital-to-analog converter in a first feedback loop, and an active filter having a large gain factor in a second feedback loop around the passive delta-sigma modulator.

Signal conversion of an input signal can be achieved by processing portions of the signal through plural parallel paths, which collectively approximate a desired infinite impulse response (IIR) filter, either alone or implemented with other signal processing functions. In one aspect, each of the paths can perform filtering, noise-shaping and / or quantization on a respective portion of the input signal to provide a corresponding representation of the respective portion of the input signal, for example, a coarser representation at a higher data rate. The corresponding representations from the parallel paths can be aggregated and further processed in a desired manner, such as conversion to an analog signal.

A method and apparatus to receive and demodulate call related information, e.g., Caller ID information, in an audio codec placed on the line side and powered by current drawn from the telephone line. The audio codec includes a 1st order SIGMA / DELTA A / D converter to digitize the signal from the telephone line with SIGMA / DELTA modulation. The 1st order SIGMA / DELTA A / D converter may be a scaleable component capable of alternative operation in a 2nd order. The SIGMA / DELTA encoded digitized signal is digitally processed by a DSP including an amplifier module, a digital filter, a limit / slice module, and an FSK decoder to receive and output the call related information. Placement of the audio codec on the line side and the scaleable SIGMA / DELTA A / D converter provides significantly reduced power requirements for the audio codec, thus allowing operation from power derived from the telephone line. In another embodiment, to further reduce power consumption of the audio codec, the 1st order SIGMA / DELTA A / D converter is sampled at a slower rate than is conventional, e.g., by first dividing or otherwise providing a slower sampling clock.

The present invention relates to a method for providing an improved generated arbitrary waveform using a sigma-delta modulator with pulse width modulation, said method comprising the steps of sigma-delta modulation of said generated arbitrary waveform, and pulse width modulation of the output signal of said sigma-delta modulator, introducing a minimum pulse width (pwmin) during said pulse width modulation.

Stable, robust, and high-resolution delta-sigma error feedback modulators, such as those used in digital-to-analog converters and phase-locked loops, include an L-order noise transfer function that is provided with L+1 high-order bits from a truncation element. The stability of such delta-sigma error feedback modulators is independent of the input signal. Moreover, the out-of-band gain of the noise transfer function need not be limited, which improves the resolution and the signal-to-noise ratio of the in-band signal.

An image-sensing element has an array of photodiodes or other photodetecting elements and performs sigma-delta analog-to-digital conversion on the outputs of the photodetecting elements. The sigma-delta analog-to-digital converters have components divided between pixel-level and row-level structures, with each row-level structure connected to its pixel-level structures to define a multiplexed-input-separated sigma-delta analog-to-digital converter. The converter can include an integrator or can rely on an integration effect of the photodetecting element. The feedback required for sigma-delta analog-to-digital conversion can involve digital-to-analog converters located at each row-level structure or at each pixel-level structure.

The invention discloses a system and method for improving the out-of-band noise response of a multi-order delta-sigma modulator. The system and method includes programmable delta-sigma modulators which may be programmed to vary the reference signals at each modulator stage subsequent to the first stage relative to the reference signal of the first modulator stage. The resulting signal output will then typically exhibit the enhanced noise suppression characteristics of a dithered signal without the added circuitry and power required of a dithering apparatus.

A multi-bit sigma-delta analog to digital converter has a quantizer, a loop filter circuit, and a digital to analog feedback circuit. The quantizer, loop filter, and digital to analog feedback circuit have a loop gain associated therewith. The quantizer and loop filter have a combined gain associated therewith. The full-scale of the digital to analog feedback circuit is varied. The combined gain of the quantizer and loop filter is also varied. More specifically, the combined gain of the quantizer and loop filter is varied in inverse proportion to the full-scale of the digital to analog feedback circuit to maintain the loop gain at a substantially constant level.

Sigma-delta modulation is provided, comprising feeding an input signal to a first SDM, subtracting the output of the first SDM from the input signal, filtering the output of the subtracting to obtain a filtered signal, delaying the input signal, adding the filtered signal to the delayed signal, feeding the output of the adder to a second SDM and providing the output of the second SDM. The first SDM in combination with the subtracting and filtering delivers a correction signal which, by adding it to the input signal, reduces the distortion in the second SDM, which second SDM performs in fact the sigma-delta modulation of the device.

A digital / analog conversion apparatus for converting a digital signal into an analog signal. The digital / analog conversion apparatus can generate a high-quality analog signal, even when elements configuring the digital / analog conversion apparatus have variance, with high resolution and a small circuit size. The data conversion apparatus is provided with a first data converter for reducing the number of bits of an input signal, a second data converter for converting the format of the first output signal, and a third data converter for conversion into a code which corresponds to the history of the output from the second data converter.

A method and apparatus are provided for reducing distortion in a dynamically delayed digital sample stream of an imaging system. The method includes the steps of delta-sigma modulating an input analog signal of the imaging system at a frequency above the Nyquist frequency of the input analog signal to generate a digital sample stream and changing a length of the sample stream to delay a portion of the sample stream while maintaining synchronism between a delta-sigma modulator and a demodulator of the system.

A method and apparatus are provided for reducing distortion in a dynamically delayed digital sample stream of an imaging system. The method includes the steps of delta-sigma modulating an input analog signal of the imaging system at a frequency above the Nyquist frequency of the input analog signal to generate a digital sample stream and changing a length of the sample stream to delay a portion of the sample stream while maintaining synchronism between a delta-sigma modulator and a demodulator of the system.

A delta-sigma modulator circuit includes an n-level quantizer circuit that is configured to generate a quantized output signal responsive to an input signal. The n-level quantizer circuit includes n adder circuits that are configured to add a dither signal to n quantization levels to generate n dithered quantization levels, respectively and n comparator circuits that are configured to compare the input signal with the n dithered quantization levels to generate the quantized output signal.