Due to significant manufacturing process variations, the performance of integrated circuits (ICs) has become increasingly uncertain. Such uncertainties must be carefully quantified with efficient stochastic circuit simulators. This paper discusses the ...

In this paper, we describe a novel statistical framework, referred to as Bayesian Model Fusion (BMF), that allows us to minimize the simulation and/or measurement cost for both pre-silicon validation and post-silicon tuning of analog and mixed-signal (...

In high-level designs, variables are often naturally represented in a symbolic multi-valued form. Binary encoding is an essential step in realizing these designs in Boolean circuits. This paper poses the encoding problem with the objective of maximizing ...

Length-matching is an important technique to balance delays of bus signals in high-performance PCB routing. Existing routers, however, may generate dense meander segments with small distance. Signals propagating across these meander segments exhibit a ...

Recently, to cope with clock TSV (Through-Silicon-Via) reliability problem efficiently, a new circuit structure called TSV Fault-tolerant Unit (TFU) and the allocation method of TFUs have been proposed. However, the existing design methods partially or ...

This work proposes a novel latch placement methodology by computing optimized placement templates with significantly lower local clock tree capacitance at a one-time cost per standard cell library. By directly minimizing local clock tree capacitance, ...

A symmetric-function fanin tree (SFFT) is a fanout-free cone of logic that computes a symmetric function such as AND, OR and XOR. These trees are usually created during logic synthesis, when there is no knowledge of the tree gate locations. Because of ...

In this paper we discuss the potential of emerging spin-torque devices for computing applications. Recent proposals for spin-based computing schemes may be differentiated as 'all-spin' vs. hybrid, programmable vs. fixed, and, Boolean vs. non-Boolean. ...

In the past decades, harmonic balance (HB) has been widely used for computing steady-state solutions of nonlinear radio-frequency (RF) and microwave circuits. However, using HB for simulating strongly nonlinear RF circuits still remains a very ...

Accurately estimating the rare failure rates for nanoscale circuit blocks (e.g., SRAM, DFF, etc.) is a challenging task, especially when the variation space is high-dimensional. In this paper, we propose a novel scaled-sigma sampling (SSS) method to ...

Hardware acceleration is a critical component in any modern functional verification methodology. To achieve the best possible utilization, a compiler must intelligently map a logical netlist to the various resources available in the machine ...

We introduce a generalized, efficient, and accurate power abstraction model and generation techniques for complex IP blocks. This is based on the contributor based power modeling concept, which exploits the nature of power consuming components in a ...

The relentless technology scaling has led to significantly reduced noise margin and complicated functionalities. As such, design time techniques per se are less likely to ensure power integrity, resulting in runtime voltage emergencies. To alleviate the ...

We present a silicon implementation of a hardware Trojan, which is capable of leaking the secret key of a wireless cryptographic integrated circuit (IC) consisting of an Advanced Encryption Standard (AES) core and an Ultra-Wide-Band (UWB) transmitter. ...

Testing flat panel display source driver ICs is a costly process; the root cause is the internal DAC array which is functionally tested. This paper proposes an IDDQ-based design-for-test (DFT) technique to detect the open and short faults inside the DAC ...

Electromigration (EM) in power distribution network (PDN) is a major reliability issue in 3D ICs. While the EM issues of local vias and through-silicon-vias (TSV) have been studied separately, the interplay of TSVs and conventional local vias in 3D ICs ...

The CTE mismatch-induced stress in 3D ICs may initiate cracks from the interface between a TSV and its dielectric liner, and propagates them on the silicon substrate surface. If a crack grows beyond the keep-out-zone (KOZ) of a TSV, it will jeopardize ...

In this paper, we present a transient modeling of electromigration (EM) in TSV and TSV-to-wire interfaces in the power delivery network (PDN) of 3D ICs. In particular, we model atomic depletion and accumulation, effective resistance degradation, and ...

A new quadratic global placer called POLAR is proposed. POLAR is based on novel techniques for rough legalization and wirelength refinement. During look-ahead rough legalization (LAL), relative positions of cells are maintained as they are relocated ...

As the feature size of semiconductor process further scales to sub-16nm technology node, triple patterning lithography (TPL) has been regarded one of the most promising lithography candidates. M1 and contact layers, which are usually deployed within ...