Place and route for massively parallel hardware-accelerated functional verification
Abstract
Hardware acceleration is a critical component in any modern functional verification methodology. To achieve the best possible utilization, a compiler must intelligently map a logical netlist to the various resources available in the machine architecture. For instance, instructions that serve to route signals between processors must be carefully balanced with those that encode Boolean operations. In addition, chip-to-chip communication should be reduced whilst also ensuring that logic is appropriately partitioned to be executed concurrently. This process is exacerbated by hard constraints on accelerator capacity, as well as rapidly growing industrial designs that approach billions of gates in size. In this paper, we present several compilation strategies that optimize resource allocation to curtail simulation depth, leverage design hierarchy to reduce runtime and memory, and exploit parallel processing to further improve performance. We also review the history of hardware acceleration within IBM, and describe the evolution in architecture that has driven many of these advances in compilation.
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- Place and route for massively parallel hardware-accelerated functional verification
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Published: 18 November 2013
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November 18 - 21, 2013
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