SIGARCH

The main intent of this paper will be the description of a multiprocessor system that uses microprogrammed hardware to support operating system primitives that contribute to its high performance vector processing capability. The system consists of nodes ...

The Pringle is a 64 processor MIMD computer with a 64 M (8 bit) instructions per second execution rate. (Copies are running at Purdue and Washington.) The Pringle runs programs written for the Configurable, Highly Parallel (CHiP) Computer. That is, the ...

A novel implementation of a Two-dimensional FFT array processor is given. The reasons for its superior performance is the one-to-one and onto mapping of the problem communications topology onto the interconnection network, VLSI-based implementation, a ...

REPLICA is a special-purpose computer architecture to support active multi-sensory perception of 3-D objects. The system is partitionable, reconfigurable, and highly parallel. In this paper, we present the design of a set of interconnection networks ...

A multiprocessor architecture has been developed which addresses the problem of the display and manipulation of multiple shaded three dimensional objects derived from emperical data on a raster scan CRT. Fully general control of such parameters as ...

A new special purpose processor, named MN8614, has been developed for the high speed execution of binary image transformations. The processor carrys out the processing based on a new extension of the DDA algorithm to reduce the number of multiplications ...

In this paper, we report the status of study on MANIP, a parallel computer for solving combinatorial extremum-search problems. The most general technique that can be used to solve a wide variety of these problems on a uniprocessor system, optimally or ...

This paper describes the basic principles, the architecture and the applications of a processor called the SCHUSS filter*.

The SCHUSS filter can be seen as a device with two inputs and one output; the first input is the filtering criterion (a program); ...

Communication is a basic problem when using VLSI technology to implement large parallel circuits. Valuable chip area must be used to run wires connecting components on a chip and current packaging technology restricts the amount of communication that ...

Performance evaluation, using both analytical and simulation models, of circuit switching baseline networks is presented. Two configurations of the baseline networks, single and dual, are evaluated. In each configuration, two different conflict ...

We present a theory that defines performance of packet-switching interconnection networks (delay and capacity) and their cost in terms of their geometry. This is used to prove that square banyan networks have optimal performance/cost ratio. These ...

Packet switched Multistage Interconnection Networks (MINs) have been mostly proposed to use unique connection path between any source and destination. We propose to add a few extra stages in an MIN to create multiple paths between any source and ...

Basic principles and design tradeoffs for control of pipelined processors are first discussed. We concentrate on register-register architectures like the CRAY-1 where pipeline control logic is localized to one or two pipeline stages and is referred to ...

This paper presents a technique for specifying change of control (e.g. branch) commands at a sequential processor's macroinstruction set level. It is shown that by representing high level language (HLL) control statements with special machine language ...

In this paper we show how to execute in parallel loops containing IF statements. We give an architectural model of parallel computation and describe the design of a hardware Boolean Recurrence Solver. Our method of handling such loops is then compared ...

This paper outlines the overall architecture of a query processor for relational queries and describes the design and control of its major processing modules. The query processor consists of only four processing modules and a number of random-access ...

A binary tree machine which can handle all the dictionary machine and priority queue operations as well as some other data queries is designed in this paper. This machine supports operations like Insert, Delete, Extract-Min/Max, Membership and Near and ...

A number of tree-structured multiprocessor designs have been proposed for performing a group of dictionary operations (INSERT, DELETE, EXTRACTMIN, NEAR, etc.) on a set of keys. These designs typically use one processor for each key stored and operate ...

Advances in integrated circuit density are permitting the implementation on a single chip of functions and performance enhancements beyond those of a basic processors. One performance enhancement of proven value is a cache memory; placing a cache on the ...

The Static Column RAM devices recently introduced offer the potential for implementing a direct-mapped cache on-chip with only a small increase in complexity over that needed for a conventional dynamic RAM memory system. Trace-driven simulation shows ...

This paper proposes a new object model, called the distributed object model, wherein the model is unified as a protection unit, as a method of data abstraction, and as a computational unit, so as to realize reliable, maintainable, and secure systems. An ...

Smalltalk on a RISC (SOAR) is a simple, Von Neumann computer that is designed to execute the Smalltalk-80 system much faster than existing VLSI microcomputers. The Smalltalk-80 system is a highly productive programming environment but poses tough ...

Conventional instruction sets or directly interpretable languages (DILs) have not been designed with high-level languages (HLLs) in mind. The modern design problem is to derive a space-time efficient DIL for a HLL processing system. In this paper, we ...

We describe a systematic method for the design of systolic arrays. This method may be used for algorithms that can be expressed as a set of uniform recurrent equations over a convex set D of Cartesian coordinates. Most of the algorithms already ...

In this paper the problem of computing the Discrete Fourier Transform (DFT) in VLSI is considered. We describe an approach to extend the linear systolic array algorithm to the multidimensional systolic network algorithm. The proposed networks is based ...

A major problem in executing algorithms in array processors is the implementation of broadcasts without unnecessary speed-up factor degradation. We discuss when and how broadcasts can be eliminated or reduced to easily implementable sequences of reduced ...

A matrix-multiplication algorithm on a linear array using an optimal number of processing elements is proposed. The local storage required by the processing elements and the I/O bandwidth required to drive the array are both constants that are ...

Unidirectional error protecting codes for VLSI memories are described. After developing the theory of unidirectional error detection and correction, optimal systematic codes capable of detecting unidirectional errors are presented. Efficient single ...