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The use of static column ram as a memory hierarchy

Authors:

James R. Goodman,

Men-chow ChiangAuthors Info & Claims

ACM SIGARCH Computer Architecture News, Volume 12, Issue 3

Pages 167 - 173

https://doi.org/10.1145/773453.808179

Published: 01 January 1984 Publication History

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Abstract

The Static Column RAM devices recently introduced offer the potential for implementing a direct-mapped cache on-chip with only a small increase in complexity over that needed for a conventional dynamic RAM memory system. Trace-driven simulation shows that such a cache can only be marginally effective if used in the obvious way. However it can be effective in satisfying the requests from a processor containing an on-chip cache. The SCRAM cache is more effective if the processor cache handles both instructions and data.

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Cited By

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Cuppu VJacob BDavis BMudge T(2001)High-Performance DRAMs in Workstation EnvironmentsIEEE Transactions on Computers10.1109/12.96649150:11(1133-1153)Online publication date: 1-Nov-2001
https://dl.acm.org/doi/10.1109/12.966491
Mogalle MMogalle M(2001)Von der systembezogenen Umweltforschung zur transdisziplinären NachhaltigkeitsforschungManagement transdisziplinärer Forschungsprozesse10.1007/978-3-0348-8249-1_3(15-54)Online publication date: 2001
https://doi.org/10.1007/978-3-0348-8249-1_3
Cuppu VJacob BDavis BMudge T(2001)High-Performance DRAMs in Workstation EnvironmentsIEEE Transactions on Computers10.1109/12.96649150:11(1133-1153)Online publication date: 1-Nov-2001
https://dl.acm.org/doi/10.1109/12.966491
Show More Cited By

Index Terms

The use of static column ram as a memory hierarchy
1. Hardware
  1. Integrated circuits
    1. Semiconductor memory
      1. Dynamic memory
      2. Static memory

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Information & Contributors

Information

Published In

cover image ACM SIGARCH Computer Architecture News

ACM SIGARCH Computer Architecture News Volume 12, Issue 3

June 1984

348 pages

ISSN:0163-5964

DOI:10.1145/773453

Issue’s Table of Contents

ISCA '84: Proceedings of the 11th annual international symposium on Computer architecture
January 1984
373 pages
ISBN:0818605383
DOI:10.1145/800015
Chairman:
Dharma P. Agrawal

Publisher

Association for Computing Machinery

New York, NY, United States

Publication History

Published: 01 January 1984

Published in SIGARCH Volume 12, Issue 3

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Cited By

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Cuppu VJacob BDavis BMudge T(2001)High-Performance DRAMs in Workstation EnvironmentsIEEE Transactions on Computers10.1109/12.96649150:11(1133-1153)Online publication date: 1-Nov-2001
https://dl.acm.org/doi/10.1109/12.966491
Mogalle MMogalle M(2001)Von der systembezogenen Umweltforschung zur transdisziplinären NachhaltigkeitsforschungManagement transdisziplinärer Forschungsprozesse10.1007/978-3-0348-8249-1_3(15-54)Online publication date: 2001
https://doi.org/10.1007/978-3-0348-8249-1_3
Cuppu VJacob BDavis BMudge T(2001)High-Performance DRAMs in Workstation EnvironmentsIEEE Transactions on Computers10.1109/12.96649150:11(1133-1153)Online publication date: 1-Nov-2001
https://dl.acm.org/doi/10.1109/12.966491
Chiueh T(1992)A case for Wafer-scale interconnected memory arraysProceedings of the 1992 ACM/IEEE conference on Supercomputing10.5555/147877.148050(468-477)Online publication date: 1-Dec-1992
https://dl.acm.org/doi/10.5555/147877.148050
Kessler RHill M(1992)Page placement algorithms for large real-indexed cachesACM Transactions on Computer Systems10.1145/138873.13887610:4(338-359)Online publication date: 1-Nov-1992
https://dl.acm.org/doi/10.1145/138873.138876
Chiueh T(1992)A case for wafer-scale interconnected memory arraysProceedings Supercomputing '9210.1109/SUPERC.1992.236657(468-477)Online publication date: 1992
https://doi.org/10.1109/SUPERC.1992.236657
Arimoto KAsakura MHidaka HMatsuda YFujishama K(1991)A circuit design of intelligent cache DRAM with automatic write-back capabilityIEEE Journal of Solid-State Circuits10.1109/4.7505526:4(560-565)Online publication date: Apr-1991
https://doi.org/10.1109/4.75055
Hidaka HMatsuda YAsakura MFujishima K(1990)The Cache DRAM ArchitectureIEEE Micro10.1109/40.5294410:2(14-25)Online publication date: 1-Mar-1990
https://dl.acm.org/doi/10.1109/40.52944
Asakura MMatsuda YHidaka HTanaka YFujishima K(1990)An experimental 1-Mbit cache DRAM with ECCIEEE Journal of Solid-State Circuits10.1109/4.5027625:1(5-10)Online publication date: Jan-1990
https://doi.org/10.1109/4.50276
Ward SZak R(1988)Set-associative dynamic random access memoryProceedings 1988 IEEE International Conference on Computer Design: VLSI10.1109/ICCD.1988.25747(478-483)Online publication date: 1988
https://doi.org/10.1109/ICCD.1988.25747
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