Formal approach for the safety assessment of embedded controller based on programmable electronic hardware
Method gives assurance when system development or service history data not available.Approach shown on embedded control system having legacy components.Formal models created from available system description.Safety assessment performed using analysis of ...
Matrix computing coprocessor for an embedded system
Matrix computing based on software, particularly floating point matrix computing, is slow and often becomes a problem in overall embedded systems. A matrix computing coprocessor (MCC) is developed in this study to improve the performance of matrix ...
Combining execution pipelines to improve parallel implementation of HMMER on FPGA
HMMER is a widely used tool in bioinformatic, based on the Profile Hidden Markov Models. The computation kernels of HMMER, namely MSV and P7Viterbi are very compute intensive, and their data dependencies if interpreted naively, lead to a purely ...
Thread-level synthetic benchmarks for multicore systems
One of the commonly used techniques to speedup early architectural exploration and performance evaluation of new hardware architectures is to use synthetic benchmarks. This paper presents a novel automated thread-level synthetic benchmark generation ...
An ultra-high throughput and fully pipelined implementation of AES algorithm on FPGA
We propose high throughput AES implementations in ECB and CTR modes.S-box is efficiently implemented by combining memory and non-memory based approaches.We achieve area-delay efficient multipliers and multiplicative inverters in GF(28).We employ loop-...
Analysis of the efficiency of the census transform algorithm implemented on FPGA
Over the course of the last two decades, continuous advances in the stereo vision field have been documented. In this paper we present an analysis of the efficiency for the stereo vision algorithm of the Census Transform algorithm. In addition to the ...
ARM-based arrhythmia beat monitoring system
This paper aims for accurate diagnosis of arrhythmia beats in real time to enhance the health care service for cardiovascular diseases. The proposed methodology for the diagnosis involves the integration of the R-peak detection algorithm, FFT (fast ...
Designing quantum-dot cellular automata counters with energy consumption analysis
Quantum-dot cellular automata (QCA) exhibits a new paradigm at nanoscale for possible substitution of conventional CMOS technology. Most of the research works in QCA domain have completely ignored the significance of energy consumption constraint in ...
Design of an efficient dual mode reconfigurable FIR filter architecture in speech signal processing
Modern Digital Signal Processing systems require the reconfigurable FIR filters with low complexity architectures. This paper presents a novel architecture for low power and low area implementation of reconfigurable Finite Impulse Response (FIR) filter ...
P2IP
This paper presents a novel systolic Coarse-Grained Reconfigurable Architecture for real-time image and video processing called P2IP. The P2IP is a scalable architecture that combines the low-latency characteristic of systolic array architectures with a ...
SAccO
This paper presents SAccO (Scalable Accelerator platform Osnabrück), a novel framework for implementing data-intensive applications using scalable and portable reconfigurable hardware accelerators. Instead of using expensive "reconfigurable ...
ASTRO
Emerging integrated CPU+FPGA hybrid platforms, such as the Extensible Processing Platform architecture from Xilinx 1, offer unprecedented opportunity to achieving both multifunctionality and real-time responsiveness for memory-intensive embedded ...
FPGA-GPU communicating through PCIe
In recent years two main platforms emerged as powerful key players in the domain of parallel computing: GPUs and FPGAs. Many researches investigate interaction and benefits of coupling them with a general purpose processor (CPU), but very few, and only ...
Processor arrays generation for matrix algorithms used in embedded platforms implemented on FPGAs
Matrix algorithms are an important part of many digital signal processing applications as they are core kernels that are usually required to be applied many times while computing different tasks. Hardware assisted implementations using FPGAs provide a ...
Hardware/software co-design of physical unclonable function based authentications on FPGAs
Physical Unclonable Functions (PUFs) enable the generation of device-unique, on-chip, and digital identifiers by exploiting the manufacturing process variation. The past decade has seen an extensive effort in PUF design. Yet, most PUF constructions are ...