IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Recent research has demonstrated that for certain types of applications like sampled audio systems, self-timed circuits can achieve very low power consumption, because unused circuit parts automatically turn into a stand-by mode. Additional savings may ...

Adiabatic switching is an approach to low-power digital circuits that differs fundamentally from other practical low-power techniques. When adiabatic switching is used, the signal energies stored on circuit capacitances may be recycled instead of ...

In this paper, we study the simultaneous driver and wire sizing (SDWS) problem under two objective functions: i) delay minimization only, or ii) combined delay and power dissipation minimization. We present general formulations of the SDWS problem under ...

We address the problem of optimizing logic-level sequential circuits for low power. We present a powerful sequential logic optimization method that is based on selectively precomputing the output logic values of the circuit one clock cycle before they ...

Embedded computer systems are characterized by the presence of a dedicated processor and the software that runs on it. Power constraints are increasingly becoming the critical component of the design specification of these systems. At present, however, ...

With the advent of portable and high-density microelectronic devices, the power dissipation of very large scale integrated (VLSI) circuits is becoming a critical concern. Accurate and efficient power estimation during the design phase is required in ...

In integer linear programming (ILP), formulating a "good" model is of crucial importance to solving that model. In this paper, we begin with a mathematical analysis of the structure of the assignment, timing, and resource constraints in high-level ...

In this paper, the design of a C-testable, high-performance carry-free array divider is presented. A radix-2 redundant number based carry-free divider is considered and is modified to make it C-testable, i.e., it can be exhaustively tested using a ...

A contemporary definition of VLSI placement problem is characterized by multiple objectives. These objectives are: timing, chip area, interconnection length and possibly others. In this paper, fuzzy logic has been used to facilitate multiobjective ...

This paper considers automatic synthesis of segmented channel architecture of row-based FPGA's so as to achieve maximum routability and performance. The routability of a channel and the performance of the routed nets may have conflicting requirements. ...

Testing screens for good chips. However, when test fall out is high (low yield) it becomes necessary to diagnose faults so that the manufacturing process or physical design can be filed to improve yield. Several scan based diagnostic schemes are used in ...

The effect of compensating module faults on the reliability of majority voting based VLSI fault-tolerant circuits is investigated using a fault injection simulation method. This simulation method facilitates consideration of multiple faults in the ...

The Booth multiplication algorithm produces incorrect results for some word sizes, when it is extended for higher radix, fixed-point multiplication. We present a modification of the Booth algorithm that produces correct results when the radix is any ...

This paper presents two novel sorting network-based architectures for computing high sample rate nonrecursive rank order filters. The proposed architectures consist of significantly fewer comparators than existing sorting network-based architectures ...