Nothing Special   »   [go: up one dir, main page]

skip to main content
Volume 11, Issue 2June 2018
Editor:
  • Steve Wilton
Publisher:
  • Association for Computing Machinery
  • New York
  • NY
  • United States
ISSN:1936-7406
EISSN:1936-7414
Reflects downloads up to 10 Nov 2024Bibliometrics
Skip Table Of Content Section
research-article
Framework for Rapid Performance Estimation of Embedded Soft Core Processors
Article No.: 9, Pages 1–21https://doi.org/10.1145/3195801

The large number of embedded soft core processors available today make it tedious and time consuming to select the best processor for a given application. This task is even more challenging due to the numerous configuration options available for a ...

research-article
Preemption of the Partial Reconfiguration Process to Enable Real-Time Computing With FPGAs
Article No.: 10, Pages 1–24https://doi.org/10.1145/3182183

To improve computing performance in real-time applications, modern embedded platforms comprise hardware accelerators that speed up the task’s most compute-intensive parts. A recent trend in the design of real-time embedded systems is to integrate field-...

research-article
Wotan: Evaluating FPGA Architecture Routability without Benchmarks
Article No.: 11, Pages 1–23https://doi.org/10.1145/3195800

FPGA routing architectures consist of routing wires and programmable switches that together account for the majority of the fabric delay and area, making evaluation and optimization of an FPGA’s routing architecture very important. Routing architectures ...

research-article
Reconfigurable Hardware Architecture for Authenticated Key Agreement Protocol Over Binary Edwards Curve
Article No.: 12, Pages 1–19https://doi.org/10.1145/3231743

In this article, we present a high-performance hardware architecture for Elliptic curve based (authenticated) key agreement protocol “Elliptic Curve Menezes, Qu and Vanstone” (ECMQV) over Binary Edwards Curve (BEC). We begin by analyzing inversion ...

research-article
Automated Synthesis of Streaming Transfer Level Hardware Designs
Article No.: 13, Pages 1–22https://doi.org/10.1145/3243930

As modern field-programmable gate arrays (FPGA) enable high computing performance and efficiency, their programming with low-level hardware description languages is time-consuming and remains a major obstacle to their adoption. High-level synthesis ...

Subjects

Comments

Please enable JavaScript to view thecomments powered by Disqus.