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Fine-grained acceleration using runtime integrated custom execution (RICE): work-in-progress

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CASES '19: Proceedings of the International Conference on Compliers, Architectures and Synthesis for Embedded Systems Companion

Article No.: 2, Pages 1 - 2

https://doi.org/10.1145/3349569.3351536

Published: 13 October 2019 Publication History

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Abstract

Runtime Integrated Custom Execution (RICE) relocates traditional peripheral reconfigurable acceleration devices into the pipeline of the processor. This relocation unlocks fine-grained acceleration previously impeded by communication overhead to a peripheral accelerator. Preliminary simulation results on a subset of the PARSEC benchmark suite shows promise for RICE in HPC applications.

References

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Christian Bienia. 2011. Benchmarking Modern Multiprocessors. Ph.D. Dissertation. Princeton University.

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Liang Chen, Joseph Tarango, Tulika Mitra, and Philip Brisk. 2013. A Just-in-Time Customizable processor. In Proceedings of the IEEE/ACM International Conference on Computer-Aided Design.

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Man-Lap Li, Ruchira Sasanka, Sarita V. Adve, Yen-Kuang Chen, and Eric Debes. 2005. The ALPBench Benchmark Suite for Complex Multimedia Applications. IEEE International Symposium on Workload Characterization (2005).

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Matthew A. Watkins and David H. Albonesi. 2010. ReMAP: A Reconfigurable Heterogeneous Multicore Architecture. In Proceedings of the IEEE/ACM International Symposium on Microarchitecture.

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Index Terms

Fine-grained acceleration using runtime integrated custom execution (RICE): work-in-progress
1. Computer systems organization
  1. Architectures
    1. Other architectures
      1. Reconfigurable computing
2. Hardware
  1. Integrated circuits
    1. Reconfigurable logic and FPGAs
      1. Hardware accelerators

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CASES '19: Proceedings of the International Conference on Compliers, Architectures and Synthesis for Embedded Systems Companion

October 2019

26 pages

ISBN:9781450369251

DOI:10.1145/3349569

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than the author(s) must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected].

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Association for Computing Machinery

New York, NY, United States

Publication History

Published: 13 October 2019

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ESWEEK '19

ESWEEK '19: Fifteenth Embedded Systems Week

October 13 - 18, 2019

New York, New York

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Index Terms

Recommendations

Hardware acceleration of graphics and imaging algorithms using FPGAs

A Reconfigurable Architecture for Binary Acceleration of Loops with Memory Accesses

Fingerprint image processing acceleration through run-time reconfigurable hardware

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