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- ArticleSeptember 2024
Cips: The Cache Intrusion Prevention System
AbstractCaches are an essential component in the performance-driven memory hierarchy of modern CPUs. However, they are also known to be vulnerable against a variety of timing side-channel attacks like Prime+Probe, Flush+Reload, and others. These allow ...
- research-articleDecember 2023
MVC: Enabling Fully Coherent Multi-Data-Views through the Memory Hierarchy with Processing in Memory
MICRO '23: Proceedings of the 56th Annual IEEE/ACM International Symposium on MicroarchitecturePages 800–814https://doi.org/10.1145/3613424.3623784Fusing computation and memory through Processing-in-Memory (PIM) provides a radical solution to the memory wall problem by minimizing communication overheads for data-intensive tasks, leading to a revolutionary shift in computer architecture. Although ...
- research-articleAugust 2023
Re-Cache: Mitigating cache contention by exploiting locality characteristics with reconfigurable memory hierarchy for GPGPUs
AbstractModern GPGPUs have employed multi-threading to hide the long off-chip memory access latency caused by frequent cache misses. However, the limited cache capacity shared by thousands of concurrently running warps will introduce serious cache ...
- research-articleJanuary 2023
Hacky Racers: Exploiting Instruction-Level Parallelism to Generate Stealthy Fine-Grained Timers
ASPLOS 2023: Proceedings of the 28th ACM International Conference on Architectural Support for Programming Languages and Operating Systems, Volume 2Pages 354–369https://doi.org/10.1145/3575693.3575700Side-channel attacks pose serious threats to many security models, especially sandbox-based browsers. While transient-execution side channels in out-of-order processors have previously been blamed for vulnerabilities such as Spectre and Meltdown, we ...
- ArticleDecember 2021
Parallel Cache Prefetching for LSM-Tree Based Store: From Algorithm to Evaluation
Algorithms and Architectures for Parallel ProcessingPages 222–236https://doi.org/10.1007/978-3-030-95384-3_15AbstractThe Log-Structured Merge-Tree has efficient writing performance and performs well in big data scenarios. An LSM-tree transforms random writes into batch sequential writes through the design of a multilayer storage structure. However, as the core ...
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- ArticleOctober 2021
Diminisher: A Linux Kernel Based Countermeasure for TAA Vulnerability
Computer Security. ESORICS 2021 International WorkshopsPages 477–495https://doi.org/10.1007/978-3-030-95484-0_28AbstractTSX Asynchronous Abort (TAA) vulnerability is a class of Side-Channel Attack (SCA) that allows an application to leak data from internal CPU buffers through asynchronous Transactional Synchronization Extension (TSX) aborts that are exploited by ...
- research-articleMay 2022
Efficient Cache Utilization via Model-aware Data Placement for Recommendation Models
MEMSYS '21: Proceedings of the International Symposium on Memory SystemsArticle No.: 2, Pages 1–11https://doi.org/10.1145/3488423.3519317Deep neural network (DNN) based recommendation models (RMs) represent a class of critical workloads that are broadly used in social media, entertainment content, and online businesses. Given their pervasive usage, understanding the memory subsystem ...
- research-articleJune 2021
Understanding Cache Compression
ACM Transactions on Architecture and Code Optimization (TACO), Volume 18, Issue 3Article No.: 36, Pages 1–27https://doi.org/10.1145/3457207Hardware cache compression derives from software-compression research; yet, its implementation is not a straightforward translation, since it must abide by multiple restrictions to comply with area, power, and latency constraints. This study sheds light ...
- research-articleNovember 2019
On the Complexity of Cache Analysis for Different Replacement Policies
Journal of the ACM (JACM), Volume 66, Issue 6Article No.: 41, Pages 1–22https://doi.org/10.1145/3366018Modern processors use cache memory, a memory access that “hits” the cache returns early, while a “miss” takes more time. Given a memory access in a program, cache analysis consists in deciding whether this access is always a hit, always a miss, or is a ...
- research-articleOctober 2019
CleanupSpec: An "Undo" Approach to Safe Speculation
MICRO '52: Proceedings of the 52nd Annual IEEE/ACM International Symposium on MicroarchitecturePages 73–86https://doi.org/10.1145/3352460.3358314Speculation-based attacks affect hundreds of millions of computers. These attacks typically exploit caches to leak information, using speculative instructions to cause changes to the cache state. Hardware-based solutions that protect against such forms ...
- research-articleOctober 2019
Touché: Towards Ideal and Efficient Cache Compression By Mitigating Tag Area Overheads
MICRO '52: Proceedings of the 52nd Annual IEEE/ACM International Symposium on MicroarchitecturePages 453–465https://doi.org/10.1145/3352460.3358281Compression is seen as a simple technique to increase the effective cache capacity. Unfortunately, compression techniques either incur tag area overheads or restrict cache block placement to only include neighboring addresses. Ideally, we should be able ...
- research-articleJune 2019
Automatic cache partitioning method for high-level synthesis
Microprocessors & Microsystems (MSYS), Volume 67, Issue CPages 71–81https://doi.org/10.1016/j.micpro.2019.02.013AbstractExisting algorithms can be automatically translated from software to hardware using High-Level Synthesis (HLS), allowing for quick prototyping or deployment of embedded designs. High-level software is written with a single main memory ...
- research-articleMay 2019
Fast key-value stores: An idea whose time has come and gone
HotOS '19: Proceedings of the Workshop on Hot Topics in Operating SystemsPages 113–119https://doi.org/10.1145/3317550.3321434Remote, in-memory key-value (RINK) stores such as Memcached [6] and Redis [7] are widely used in industry and are an active area of academic research. Coupled with stateless application servers to execute business logic and a databaselike system to ...
- research-articleJanuary 2019
Decoupled Fused Cache: Fusing a Decoupled LLC with a DRAM Cache
ACM Transactions on Architecture and Code Optimization (TACO), Volume 15, Issue 4Article No.: 65, Pages 1–23https://doi.org/10.1145/3293447DRAM caches have shown excellent potential in capturing the spatial and temporal data locality of applications capitalizing on advances of 3D-stacking technology; however, they are still far from their ideal performance. Besides the unavoidable DRAM ...
- research-articleJuly 2018
Who watches the watcher? Detecting hypervisor introspection from unprivileged guests
Digital Investigation: The International Journal of Digital Forensics & Incident Response (DIGITI), Volume 26, Issue SPages S98–S106https://doi.org/10.1016/j.diin.2018.04.015AbstractWe present research on the limitations of detecting atypical activity by a hypervisor from the perspective of a guest domain. Individual instructions which have virtual machine exiting capability were evaluated, using wall timing and ...
- research-articleSeptember 2017
Low-power content addressable memory (CAM) array for mobile devices
Microelectronics Journal (MICROJ), Volume 67, Issue CPages 10–18https://doi.org/10.1016/j.mejo.2017.07.001Large-capacity content-addressable memory (CAM) is beneficial in a variety of applications that require high-speed lookup table. It is used extensively in low power CPU design, network routers, and cache controllers. Content addressable memory system ...
- research-articleJune 2017
Rigorous analysis of software countermeasures against cache attacks
PLDI 2017: Proceedings of the 38th ACM SIGPLAN Conference on Programming Language Design and ImplementationPages 406–421https://doi.org/10.1145/3062341.3062388CPU caches introduce variations into the execution time of programs that can be exploited by adversaries to recover private information about users or cryptographic keys.
Establishing the security of countermeasures against this threat often requires ...
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ACM SIGPLAN Notices: Volume 52 Issue 6 - research-articleOctober 2015
Design Methodologies for Yield Enhancement and Power Efficiency in SRAM-Based SoCs
IEEE Transactions on Very Large Scale Integration (VLSI) Systems (ITVL), Volume 23, Issue 10Pages 2054–2064https://doi.org/10.1109/TVLSI.2014.2360319This paper comprises two new methodologies to improve yield and reduce system-on-a-chip power. The first methodology is based on faulty static random-access memory (SRAM) cells detections and cache resizing. The key advantage of this approach is that it ...
- ArticleJuly 2015
Design and Implementation of an Espionage Network for Cache-based Side Channel Attacks on AES
ICETE 2015: Proceedings of the 12th International Joint Conference on e-Business and Telecommunications - Volume 4Pages 441–447https://doi.org/10.5220/0005576804410447We design and implement the espionage infrastructure to launch a cache-based side channel attack on AES.
This includes a spy controller and a ring of spy threads with associated analytic capabilities â all hosted on a
single server. By causing the ...
- ArticleApril 2013
A rapid cache-aware procedure positioning optimization to favor incremental development
RTAS '13: Proceedings of the 2013 IEEE 19th Real-Time and Embedded Technology and Applications Symposium (RTAS)Pages 107–116https://doi.org/10.1109/RTAS.2013.6531084Truly incremental development is a holy grail of verification-intensive software industry. All factors that threaten it should be removed. Cache memories have an intrinsically jittery timing behavior. The WCET variability that this causes wrecks ...