Energy-efficient magnetic 4-2 compressor
In this paper, we present a hybrid MTJ/CMOS based low-power design of a 4-2 compressor. Furthermore, to gain more energy efficiency we implemented the proposed design with carbon nanotube field effect transistor (CNFET) technology and compared it with ...
Low-power content addressable memory (CAM) array for mobile devices
Large-capacity content-addressable memory (CAM) is beneficial in a variety of applications that require high-speed lookup table. It is used extensively in low power CPU design, network routers, and cache controllers. Content addressable memory system ...
A low-complexity locking-accelerated digital PLL with multi-output bang-bang phase detector
This paper presents a digital phase-locked-loop (DPLL) based on multi-output bang-bang phase detector (MOBBPD) with reused most significant bits (MSBs) of MOBBPD. The MOBBPD can be implemented simply while achieving the merits of both time-to-digital ...
A transimpedance amplifier for optical communication network based on active voltage-current feedback
In this paper, a new topology is proposed for designing and analyzing a transimpedance amplifier (TIA) based on active voltage-current feedback. The proposed topology reduces the input and output impedances by using a common source transistor as a ...
Minimalistic SDHC-SPI hardware reader module for boot loader applications
This paper introduces a low-footprint full hardware boot loading solution for FPGA-based Programmable Systems on Chip. The proposed module allows loading the system code and data from a standard SD card without having to re-program the whole embedded ...
SET and SEU performance of single, double, triple and quadruple-gate junctionlessFETs using numerical simulations
In this paper, the relation between the number of gates and radiation resiliency, in Junctionless (JLT) devices, is investigated using 3D-TCAD simulation. JLT Devices having single, double, triple and quadruple-gate JLTs are studied for their single-...
An efficient hardware architecture of CAVLC encoder based on stream processing
The paper presents an efficient implementation of Context-Adaptive Variable Length Coding (CAVLC) entropy encoder in H.264/AVC standard. The architecture is designed with a parallel structure targeting real-time video compression. The intensive memory ...
Exploring the short channel characteristics and performance analysis of DMDG SON MOSFET
A two-dimensional (2-D) analytical model for dual-material double gate (DMDG) Silicon-on-Nothing (SON) MOSFETs is developed to study the effect of variation of both the surface potential and threshold voltage on short channel effects (SCEs). Two ...
MTCML
This paper presents an alternative CML with shallow-depth differential logic. In the proposed methodology, the tail current is dissolved into multiple tails with total current of the parent but with shallower depth from supply or ground to the common-...
Independently tunable plus-type DDCC-based voltage-mode universal biquad filter with MISO and SIMO types
This paper presents an independently tunable voltage-mode universal biquad filter using three plus-type differential difference current conveyors (DDCC+s), two grounded capacitors, three / four grounded resistors and one floating resistor. The proposed ...
Bandwidth enlargement of CMOS TIA using on-chip T-network for patient diagnosis in biomedical application
This work concerns on CMOS based trans-impedance amplifier (TIA) where enhancing the bandwidth by using optimized on-chip T-network for biomedical diagnosis applications.The proposed TIA consists of inductive peaking components as an input stage, ...
On-Line Testing of digital VLSI circuits at Register Transfer Level using High Level Decision Diagrams
Nowadays On-Line Testing (OLT) has became one the essential technique to detect faults in digital VLSI circuits which occur during their normal operation. However, most of the works on OLT reported in the literature are at the gate level and these ...
A new ICCII based resistor-less current-mode first-order universal filter with electronic tuning capability
In this paper, a new electronically tunable current-mode (CM) first-order universal filter as a new application for inverting second-generation current conveyors (ICCIIs) is proposed. The proposed circuit is based on two ICCII and a capacitor and does ...
InP DHBT technology for power amplifiers at mm-wave frequencies
An InP Double Heterojunction Bipolar Transistor (DHBT) technology is presented for millimeter-wave power amplifiers at E-band and higher frequencies. Single- and multi-finger transistors with 0.7m emitter width and emitter lengths of 5, 7, 10m are ...
A 1.6ps 7b time to digital converter in 0.18m CMOS technology
A fine Time to Digital Converter (TDC) based on time difference amplification is proposed. A current difference based method is introduced to improve the limited input linear range of the conventional2 Time Amplifier (TA). The modified TA is used in a ...
A sub-2-dB noise figure linear wideband low noise amplifier in 0.18m CMOS
This paper presents a sub-2-dB Noise Figure (NF) wideband differential Common Gate (CG) Low Noise Amplifier (LNA) in 0.18m CMOS technology. The circuit benefits from several new techniques to improve the overall performance. A new current bleeding ...
Soft error tolerant design of combinational circuits based on a local logic substitution scheme
In this paper, a resynthesis technique is introduced in order to reduce the Soft Error Rate (SER) of combinational circuits. This technique is based on the circuit partitioning and a local logical replacement. The proposed method provides an innovative ...
An 85%-efficiency reconfigurable multiphase switched capacitor DC-DC converter utilizing frequency, switch size, and interleaving scaling techniques
A high efficiency all-CMOS switched-capacitor DC-DC converter (SC DC-DC) with frequency, switch size and interleaving scaling is proposed in order to achieve high efficiency for wireless sensors and internet of things (IOTs) applications. According to ...
Adaptive and optimum multiport readout of non-gated crossbar memory arrays
Non-gated crossbar memory arrays are becoming strong candidates to replace the current gated arrays due to their much higher density. Sneak paths are the main problem in gate-less arrays. In this paper, we analyze a three reading multiport readout ...
A multi-port low-power current mode PUF using MOSFET current-division deviation in 65nm technology
Physical unclonable function (PUF) is a promising hardware security primitive for secure key generation and chip identification. This paper proposes a multi-port and low-power PUF based on MOSFET current-division deviation. Owing to the multi-port, it ...
A novel technique for duty cycle correction for reference clocks in frequency synthesizers
Frequency Multipliers to be used with Frequency Synthesizers require duty cycle of nearly 50% and low phase noise contribution to the overall system phase noise for proper operation. In this paper, we first analyze the impact of the imperfect duty cycle ...