Design and Analysis of High Performance Heterogeneous Block-based Approximate Adders
Authors: 
Ebrahim Farahmand, Ali Mahani, Muhammad Abdullah Hanif, Muhammad ShafiqueAuthors Info & Claims
Article No.: 106, Pages 1 - 32
Abstract
Approximate computing is an emerging paradigm to improve the power and performance efficiency of error-resilient applications. As adders are one of the key components in almost all processing systems, a significant amount of research has been carried out toward designing approximate adders that can offer better efficiency than conventional designs; however, at the cost of some accuracy loss. In this article, we highlight a new class of energy-efficient approximate adders, namely, Heterogeneous Block-based Approximate Adders (HBAAs), and propose a generic configurable adder model that can be configured to represent a particular HBAA configuration. An HBAA, in general, is composed of heterogeneous sub-adder blocks of equal length, where each sub-adder can be an approximate sub-adder and have a different configuration. The sub-adders are mainly approximated through inexact logic and carry truncation. Compared to the existing design space, HBAAs provide additional design points that fall on the Pareto-front and offer a better quality-efficiency tradeoff in certain scenarios. Furthermore, to enable efficient design space exploration based on user-defined constraints, we propose an analytical model to efficiently evaluate the Probability Mass Function (PMF) of approximation error and other error metrics, such as Mean Error Distance (MED), Normalized Mean Error Distance (NMED), and Error Rate (ER) of HBAAs. The results show that HBAA configurations can provide around 15% reduction in area and up to 17% reduction in energy compared to state-of-the-art approximate adders.
References
[1]
Omid Akbari, Mehdi Kamal, Ali Afzali-Kusha, and Massoud Pedram. 2016. RAP-CLA: A reconfigurable approximate carry look-ahead adder. IEEE Transactions on Circuits and Systems II: Express Briefs 65, 8 (2016), 1089–1093.
[2]
Haider A. F. Almurib, T. Nandha Kumar, and Fabrizio Lombardi. 2016. Inexact designs for approximate low power addition by cell replacement. In Proceedings of the 2016 Design, Automation Test in Europe Conference Exhibition (DATE ’16). 660–665.
[3]
Muhammad Kamran Ayub, Muhammad Abdullah Hanif, Osman Hasan, and Muhammad Shafique. 2020. PEAL: Probabilistic error analysis methodology for low-power approximate adders. ACM Journal on Emerging Technologies in Computing Systems (JETC) 17, 1 (2020), 1–37.
[4]
Muhammad Kamran Ayub, Osman Hasan, and Muhammad Shafique. 2017. Statistical error analysis for low power approximate adders. In Proceedings of the 54th Annual Design Automation Conference 2017. 1–6.
[5]
Vincent Camus, Mattia Cacciotti, Jeremy Schlachter, and Christian Enz. 2018. Design of approximate circuits by fabrication of false timing paths: The carry cut-back adder. IEEE Journal on Emerging and Selected Topics in Circuits and Systems 8, 4 (2018), 746–757.
[6]
D. Celia, Vinita Vasudevan, and Nitin Chandrachoodan. 2018. Probabilistic error modeling for two-part segmented approximate adders. In Proceedings of the 2018 IEEE International Symposium on Circuits and Systems (ISCAS ’18). IEEE, 1–5.
[7]
Sunil Dutt, Satyabrata Dash, Sukumar Nandi, and Gaurav Trivedi. 2018. Analysis, modeling and optimization of equal segment based approximate adders. IEEE Transactions on Computers 68, 3 (2018), 314–330.
[8]
F. Ebrahimi-Azandaryani, O. Akbari, M. Kamal, A. Afzali-Kusha, and M. Pedram. 2020. Block-Based carry speculative approximate adder for energy-efficient applications. IEEE Transactions on Circuits and Systems II: Express Briefs 67, 1 (2020), 137–141. DOI:
[9]
Vaibhav Gupta, Debabrata Mohapatra, Sang Phill Park, Anand Raghunathan, and Kaushik Roy. 2011. IMPACT: IMPrecise adders for low-power approximate computing. In Proceedings of the IEEE/ACM International Symposium on Low Power Electronics and Design. IEEE, 409–414.
[10]
Vaibhav Gupta, Debabrata Mohapatra, Anand Raghunathan, and Kaushik Roy. 2012. Low-power digital signal processing using approximate adders. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 32, 1 (2012), 124–137.
[11]
Vaibhav Gupta, Debabrata Mohapatra, Anand Raghunathan, and Kaushik Roy. 2013. Low-power digital signal processing using approximate adders. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 32, 1 (2013), 124–137.
[12]
Jie Han and Michael Orshansky. 2013. Approximate computing: An emerging paradigm for energy-efficient design. In Proceedings of the 2013 18th IEEE European Test Symposium (ETS ’13). 1–6.
[13]
Muhammad Abdullah Hanif, Rehan Hafiz, Osman Hasan, and Muhammad Shafique. 2017. QuAd: Design and analysis of quality-area optimal low-latency approximate adders. In Proceedings of the 54th Annual Design Automation Conference 2017. 1–6.
[14]
Muhammad Abdullah Hanif, Rehan Hafiz, Osman Hasan, and Muhammad Shafique. 2020. PEMACx: A probabilistic error analysis methodology for adders with cascaded approximate units. In Proceedings of the 57th ACM/IEEE Design Automation Conference (DAC ’20). IEEE, 1–6.
[15]
Honglan Jiang, Jie Han, and Fabrizio Lombardi. 2015. A comparative review and evaluation of approximate adders. In Proceedings of the 25th edition on Great Lakes Symposium on VLSI. 343–348.
[16]
Honglan Jiang, Francisco Javier Hernandez Santiago, Hai Mo, Leibo Liu, and Jie Han. 2020. Approximate arithmetic circuits: A survey, characterization, and recent applications. Proceedings of the IEEE 108, 12 (2020), 2108–2135.
[17]
Georgios Karakonstantis and Kaushik Roy. 2011. Voltage over-scaling: A cross-layer design perspective for energy efficient systems. In Proceedings of the 20th European Conference on Circuit Theory and Design (ECCTD ’11). IEEE, 548–551.
[18]
Younghoon Kim, Swagath Venkataramani, Kaushik Roy, and Anand Raghunathan. 2016. Designing approximate circuits using clock overgating. In Proceedings of the 53rd Annual Design Automation Conference. 1–6.
[19]
Yongtae Kim, Yong Zhang, and Peng Li. 2013. An energy efficient approximate adder with carry skip for error resilient neuromorphic VLSI systems. In Proceedings of the IEEE/ACM International Conference on Computer-Aided Design (ICCAD ’13). IEEE, 130–137.
[20]
Philipp Klaus Krause and Ilia Polian. 2011. Adaptive voltage over-scaling for resilient applications. In Proceedings of the 2011 Design, Automation & Test in Europe. IEEE, 1–6.
[21]
Jinghang Liang, Jie Han, and Fabrizio Lombardi. 2013. New metrics for the reliability of approximate and probabilistic adders. IEEE Transactions on Computers 62, 9 (2013), 1760–1771.
[22]
Cong Liu, Jie Han, and Fabrizio Lombardi. 2015. An analytical framework for evaluating the error characteristics of approximate adders. IEEE Transactions on Computers 64, 5 (2015), 1268–1281.
[23]
Sana Mazahir, Osman Hasan, Rehan Hafiz, Muhammad Shafique, and Jörg Henkel. 2016. Probabilistic error modeling for approximate adders. IEEE Transactions on Computers 66, 3 (2016), 515–530.
[24]
Masoud Pashaeifar, Mehdi Kamal, Ali Afzali-Kusha, and Massoud Pedram. 2018. Approximate reverse carry propagate adder for energy-efficient DSP applications. IEEE Transactions on Very Large Scale Integration (VLSI) Systems 26, 11 (2018), 2530–2541.
[25]
Bharath Srinivas Prabakaran, Semeen Rehman, Muhammad Abdullah Hanif, Salim Ullah, Ghazal Mazaheri, Akash Kumar, and Muhammad Shafique. 2018. DeMAS: An efficient design methodology for building approximate adders for FPGA-based systems. In Proceedings of the Design, Automation & Test in Europe Conference & Exhibition (DATE ’18). IEEE, 917–920.
[26]
Muhammad Shafique, Waqas Ahmad, Rehan Hafiz, and Jörg Henkel. 2015. A low latency generic accuracy configurable adder. In Proceedings of the 52nd ACM/EDAC/IEEE Design Automation Conference (DAC ’15). IEEE, 1–6.
[27]
Avishek Sinha Roy, Rajdeep Biswas, and Anindya Sundar Dhar. 2020. On fast and exact computation of error metrics in approximate LSB adders. IEEE Transactions on Very Large Scale Integration (VLSI) Systems 28, 4 (2020), 876–889.
[28]
Ajay K. Verma, Philip Brisk, and Paolo Ienne. 2008. Variable latency speculative addition: A new paradigm for arithmetic circuit design. In Proceedings of the Conference on Design, Automation and Test in Europe (DATE ’08). 1250–1255.
[29]
Neil Weste and David Harris. 2010. CMOS VLSI Design: A Circuits and Systems Perspective. Pearson.
[30]
Yi Wu, You Li, Xiangxuan Ge, Yuan Gao, and Weikang Qian. 2018. An efficient method for calculating the error statistics of block-based approximate adders. IEEE Transactions on Computers 68, 1 (2018), 21–38.
[31]
Qiang Xu, Todd Mytkowicz, and Nam Sung Kim. 2015. Approximate computing: A survey. IEEE Design & Test 33, 1 (2015), 8–22.
[32]
Wenbin Xu, Sachin S. Sapatnekar, and Jiang Hu. 2018. A simple yet efficient accuracy-configurable adder design. IEEE Transactions on Very Large Scale Integration (VLSI) Systems 26, 6 (2018), 1112–1125.
[33]
Z. Yang, A. Jain, J. Liang, J. Han, and F. Lombardi. 2013. Approximate XOR/XNOR-based adders for inexact computing. In Proceedings of the 13th IEEE International Conference on Nanotechnology (IEEE-NANO ’13). 690–693.
[34]
Rong Ye, Ting Wang, Feng Yuan, Rakesh Kumar, and Qiang Xu. 2013. On reconfiguration-oriented approximate adder design and its application. In Proceedings of the IEEE/ACM International Conference on Computer-Aided Design (ICCAD ’13). IEEE, 48–54.
[35]
Ning Zhu, Wang Ling Goh, Gang Wang, and Kiat Seng Yeo. 2010. Enhanced low-power high-speed adder for error-tolerant application. In Proceedings of the 2010 International SoC Design Conference. IEEE, 323–327.
[36]
Ning Zhu, Wang Ling Goh, and Kiat Seng Yeo. 2011. Ultra low-power high-speed flexible probabilistic adder for error-tolerant applications. In Proceedings of the 2011 International SoC Design Conference. IEEE, 393–396.
[37]
Ning Zhu, Wang Ling Goh, Weija Zhang, Kiat Seng Yeo, and Zhi Hui Kong. 2009. Design of low-power high-speed truncation-error-tolerant adder and its application in digital signal processing. IEEE Transactions on Very Large Scale Integration (VLSI) Systems 18, 8 (2009), 1225–1229.
Index Terms
- Design and Analysis of High Performance Heterogeneous Block-based Approximate Adders
Recommendations
Design of approximate adders and multipliers for error tolerant image processing
AbstractAn adder is the basic computational circuit in digital Very Large Scale Integration (VLSI) design. To improve the design metrics of an adder, Approximate Adders (AAs) have been proposed. These adders have been applied and analyzed on 8 ...
Analysis and Design of Adders for Approximate Computing
Special Issue on MEMCODE 2015 and Regular Papers (Diamonds)The concept of approximate computing, that is, to sacrifice computation quality for computation efforts, has recently emerged as a promising design approach. Over the past decade, several research works have explored approximate computing at both the ...
Systematic synthesis of approximate adders and multipliers with accurate error calculations
AbstractIn this study, we perform logic synthesis and area optimization of approximate ripple-carry adders and Wallace-tree multipliers with a given error constraint. We first implement approximate 1-bit adders having different error rates as ...
Highlights- Logic synthesis and area optimization of approximate ripple-carry adders and Wallace-tree multipliers is presented.
Comments
Please enable JavaScript to view thecomments powered by Disqus.Information & Contributors
Information
Published In
November 2023
428 pages
Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than the author(s) must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected].
Publisher
Association for Computing Machinery
New York, NY, United States
Journal Family
Publication History
Published: 09 November 2023
Online AM: 28 September 2023
Accepted: 06 September 2023
Revised: 03 September 2023
Received: 24 August 2022
Published in TECS Volume 22, Issue 6
Check for updates
Author Tags
Qualifiers
- Research-article
Contributors
Other Metrics
Bibliometrics & Citations
Bibliometrics
Article Metrics
- 0Total Citations
- 181Total Downloads
- Downloads (Last 12 months)135
- Downloads (Last 6 weeks)10
Reflects downloads up to 20 Nov 2024
Other Metrics
Citations
View Options
Login options
Check if you have access through your login credentials or your institution to get full access on this article.
Sign in