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An LPDDR4 Safety Model for Automotive Applications

Published: 09 May 2022 Publication History

Abstract

The increasing demand for DRAM in modern vehicles creates new challenges for automobile manufacturers. To allow DRAM subsystems to be used in safety-critical tasks like autonomous driving, a special Automotive Safety Integrity Level (ASIL) grading according to the ISO 26262 is required. While the classification process is already well-established for processors and on-chip memories with dedicated automotive hardware introduced to the market, no similar research has been conducted for DRAM yet. As a consequence, the process proves to be difficult for car manufacturers at this point. Therefore, a methodology that captures all the DRAM subsystem complexity in a comprehensive but yet understandable way is required. In this paper we use Component Fault Trees to create a clearly-structured safety model of an exemplary LPDDR4 memory subsystem. Based on the proposed model, we also evaluate the ASIL that it can reach. For the automotive industry, our work can serve as a foundation for future classification processes, therefore taking one more step towards full autonomy.

References

[1]
Rasmus Adler, Dominik Domis, Kai Höfig, Sören Kemmann, Thomas Kuhn, Jean-Pascal Schwinn, and Mario Trapp. 2011. Integration of Component Fault Trees into the UML. In Models in Software Engineering, Juergen Dingel and Arnor Solberg (Eds.). Springer Berlin Heidelberg, Berlin, Heidelberg, 312–327.
[2]
Infineon Technologies AG. 2020. AURIX 32-bit microcontrollers for automotive and industrial applications. https://www.infineon.com/dgdl/Infineon-TriCore_Family_BR-ProductBrochure-v01_00-EN.pdf?fileId=5546d4625d5945ed015dc81f47b436c7, visited 2021-07-15.
[3]
Leonardo Bautista-Gomez, Ferad Zyulkyarov, Osman Unsal, and Simon McIntosh-Smith. 2016. Unprotected Computing: A Large-Scale Study of DRAM Raw Error Rate on a Supercomputer. In SC ’16: Proceedings of the International Conference for High Performance Computing, Networking, Storage and Analysis. 645–655. https://doi.org/10.1109/SC.2016.54
[4]
Aaron Boehm. 2021. DRAM – More Important Than You Think for Achieving Automotive Functional Safety. https://www.designnews.com/electronics/dram-more-important-you-think-achieving-automotive-functional-safety, visited 2021-07-16.
[5]
Sanguhn Cha, O. Seongil, Hyunsung Shin, Sangjoon Hwang, Kwangil Park, Seong Jin Jang, Joo Sun Choi, Gyo Young Jin, Young Hoon Son, Hyunyoon Cho, Jung Ho Ahn, and Nam Sung Kim. 2017. Defect Analysis and Cost-Effective Resilience Architecture for Future DRAM Devices. In 2017 IEEE International Symposium on High Performance Computer Architecture (HPCA). 61–72. https://doi.org/10.1109/HPCA.2017.30
[6]
Yung-Chang Chang, Li-Ren Huang, Hsing-Chuang Liu, Chih-Jen Yang, and Ching-Te Chiu. 2014. Assessing automotive functional safety microprocessor with ISO 26262 hardware requirements. In Technical Papers of 2014 International Symposium on VLSI Design, Automation and Test. 1–4. https://doi.org/10.1109/VLSI-DAT.2014.6834876
[7]
Alexander Davydov, Leonid Kaplan, Yury Smerkis, and Grigory Tauglikh. 1981. Optimization of shortened Hamming codes. Problems of Information Transmission 17 (12 1981).
[8]
Alexander Davydov and Leonid Tombak. 1991. An Alternative To The Hamming Code in The Class of SEC-DED Codes in Semiconductor Memory. Information Theory, IEEE Transactions on 37 (06 1991), 897 – 902. https://doi.org/10.1109/18.79958
[9]
Alessandro Frigerio, Bart Vermeulen, and Kees Goossens. 2019. Component-Level ASIL Decomposition for Automotive Architectures. In 2019 49th Annual IEEE/IFIP International Conference on Dependable Systems and Networks Workshops (DSN-W). 62–69. https://doi.org/10.1109/DSN-W.2019.00021
[10]
Saugata Ghose, Tianshi Li, Nastaran Hajinazar, Damla Senol Cali, and Onur Mutlu. 2019. Demystifying Complex Workload-DRAM Interactions: An Experimental Study. 93–93.
[11]
Jin-Woo Han, Jungsik Kim, Dong-Il Moon, Jeong-Soo Lee, and M. Meyyappan. 2019. Soft Error in Saddle Fin Based DRAM. IEEE Electron Device Letters 40, 4 (2019), 494–497. https://doi.org/10.1109/LED.2019.2897685
[12]
Mu-Yue Hsiao. 1970. A class of optimal minimum odd-weight-column SEC-DED codes. IBM Journal of Research and Development 14, 4 (1970), 395–401.
[13]
ISO. 2011. ISO 26262: Road vehicles – Functional safety.
[14]
Seo-Hyun Jeon, Jin-Hee Cho, Yangjae Jung, Sachoun Park, and Tae-Man Han. 2011. Automotive hardware development according to ISO 26262. In 13th International Conference on Advanced Communication Technology (ICACT2011). 588–592.
[15]
Matthias Jung, Sally A. McKee, Chirag Sudarshan, Christoph Dropmann, Christian Weis, and Norbert Wehn. 2018. Driving into the Memory Wall: The Role of Memory for Advanced Driver Assistance Systems and Autonomous Driving. In Proceedings of the International Symposium on Memory Systems (Alexandria, Virginia) (MEMSYS ’18). ACM, New York, NY, USA, 377–386. https://doi.org/10.1145/3240302.3240322
[16]
Kelly James, Synopsys, Inc.2020. Synopsys Delivers Industry’s First Processor IP Certified for Full ISO 26262 ASIL D Compliance. https://news.synopsys.com/2020-09-30-Synopsys-Delivers-Industrys-First-Processor-IP-Certified-for-Full-ISO-26262-ASIL-D-Compliance, visited 2021-07-15.
[17]
Hiroyuki Kondo, Sugako Otani, Norimasa Otsuki, Yasufumi Suzuki, Naoto Okumura, Shohei Maeda, Tomonori Yanagita, Takao Koike, Kosuke Yayama, Yasuhisa Shimazaki, Masao Ito, Minoru Uemura, Toshihiro Hattori, and Noriaki Sakamoto. 2020. A 28-nm Automotive Flash Microcontroller With Virtualization-Assisted Processor Supporting ISO26262 ASIL D. IEEE Journal of Solid-State Circuits 55, 1 (2020), 133–144. https://doi.org/10.1109/JSSC.2019.2953826
[18]
Nohhyup Kwak, Saeng-Hwan Kim, Kyong Ha Lee, Chang-Ki Baek, Mun Seon Jang, Yongsuk Joo, Seung-Hun Lee, Woo Young Lee, Eunryeong Lee, Donghee Han, Jaeyeol Kang, Jung Ho Lim, Jae-Beom Park, Kyung-Tae Kim, Sunki Cho, Sung Woo Han, Jee Yeon Keh, Jun Hyun Chun, Jonghoon Oh, and Seok Hee Lee. 2017. 23.3 A 4.8Gb/s/pin 2Gb LPDDR4 SDRAM with sub-100µA self-refresh current for IoT applications. In 2017 IEEE International Solid-State Circuits Conference (ISSCC). 392–393. https://doi.org/10.1109/ISSCC.2017.7870426
[19]
H. J. Kwon, E. Seo, C. Y. Lee, Y. H. Seo, G. H. Han, H. R. Kim, J. H. Lee, M. S. Jang, S. G. Do, S. H. Cho, J. K. Park, S. Y. Doo, J. B. Shin, S. H. Jung, H. J. Kim, I. H. Im, B. R. Cho, J. W. Lee, J. Y. Lee, K. H. Yu, H. K. Kim, C. H. Jeon, H. S. Park, S. S. Kim, S. H. Lee, J. W. Park, S. S. Lee, B. T. Lim, J. y. Park, Y. S. Park, H. J. Kwon, S. J. Bae, J. H. Choi, K. I. Park, S. J. Jang, and G. Y. Jin. 2017. 23.4 An extremely low-standby-power 3.733Gb/s/pin 2Gb LPDDR4 SDRAM for wearable devices. In 2017 IEEE International Solid-State Circuits Conference (ISSCC). 394–395. https://doi.org/10.1109/ISSCC.2017.7870427
[20]
Aanchal Lakhotia, Reuben Chang, Daryl Santos, and Christopher Greene. 2020. Fault Tree Analysis To Understand And Improve Reliability Of Memory Modules Used In Data Center Server Racks. Procedia Manufacturing 51 (01 2020), 989–997. https://doi.org/10.1016/j.promfg.2020.10.139
[21]
Kuen-Long Lu and Yung-Yuan Chen. 2019. ISO 26262 ASIL-Oriented Hardware Design Framework for Safety-Critical Automotive Systems. In 2019 IEEE International Conference on Connected Vehicles and Expo (ICCVE). 1–6. https://doi.org/10.1109/ICCVE45908.2019.8965235
[22]
Katsushige Matsubara, Lieske Hanno, Motoki Kimura, Atsushi Nakamura, Manabu Koike, Kazuaki Terashima, Shun Morikawa, Yoshihiko Hotta, Takahiro Irita, Seiji Mochizuki, Hiroyuki Hamasaki, and Tatsuya Kamei. 2021. 4.2 A 12nm Autonomous-Driving Processor with 60.4TOPS, 13.8TOPS/W CNN Executed by Task-Separated ASIL D Control. In 2021 IEEE International Solid- State Circuits Conference (ISSCC), Vol. 64. 56–58. https://doi.org/10.1109/ISSCC42613.2021.9365745
[23]
JEDEC Solid State Technology Association. 2015. Low Power Double Data Rate 3 (JESD209-3C).
[24]
JEDEC Solid State Technology Association. 2020. Low Power Double Data Rate 4 (JESD209-4C).
[25]
Hassan Mujtaba. 2018. NVIDIA Drive Xavier SOC Detailed – A Marvel of Engineering, Biggest and Most Complex SOC Design To Date With 9 Billion Transistors. https://wccftech.com/nvidia-drive-xavier-soc-detailed/, visited 2021-07-15.
[26]
Prashant J. Nair, David A. Roberts, and Moinuddin K. Qureshi. 2015. FaultSim: A Fast, Configurable Memory-Reliability Simulator for Conventional and 3D-Stacked Systems. ACM Trans. Archit. Code Optim. 12, 4, Article 44 (Dec. 2015), 24 pages. https://doi.org/10.1145/2831234
[27]
Tae-Young Oh, Hoeju Chung, Jun-Young Park, Ki-Won Lee, Seunghoon Oh, Su-Yeon Doo, Hyoung-Joo Kim, ChangYong Lee, Hye-Ran Kim, Jong-Ho Lee, Jin-Il Lee, Kyung-Soo Ha, YoungRyeol Choi, Young-Chul Cho, Yong-Cheol Bae, Taeseong Jang, Chulsung Park, Kwangil Park, SeongJin Jang, and Joo Sun Choi. 2015. A 3.2 Gbps/pin 8 Gbit 1.0 V LPDDR4 SDRAM With Integrated ECC Engine for Sub-1 V DRAM Core Operation. IEEE Journal of Solid-State Circuits 50, 1 (2015), 178–190. https://doi.org/10.1109/JSSC.2014.2353799
[28]
Minesh Patel, Jeremie Kim, Hasan Hassan, and Onur Mutlu. 2019. Understanding and Modeling On-Die Error Correction in Modern DRAM: An Experimental Study Using Real Devices. 13–25. https://doi.org/10.1109/DSN.2019.00017
[29]
Bianca Schroeder, Eduardo Pinheiro, and Wolf-Dietrich Weber. 2009. DRAM Errors in the Wild: A Large-Scale Field Study. In SIGMETRICS.
[30]
Anton Shilov. 2018. Arm Unveils Arm Safety Ready Initiative, Cortex-A76AE Processor. https://www.anandtech.com/show/13398/arm-unveils-arm-safety-ready-initiative-cortexa76ae-processor, visited 2021-07-15.
[31]
Vilas Sridharan, Nathan DeBardeleben, Sean Blanchard, Kurt B. Ferreira, Jon Stearley, John Shalf, and Sudhanva Gurumurthi. 2015. Memory Errors in Modern Systems: The Good, The Bad, and The Ugly. SIGARCH Comput. Archit. News 43, 1 (March 2015), 297–310. https://doi.org/10.1145/2786763.2694348
[32]
V. Sridharan and D. Liberty. 2012. A study of DRAM failures in the field. In High Performance Computing, Networking, Storage and Analysis (SC), 2012 International Conference for. 1–11. https://doi.org/10.1109/SC.2012.13
[33]
Vilas Sridharan, Jon Stearley, Nathan DeBardeleben, Sean Blanchard, and Sudhanva Gurumurthi. 2013. Feng Shui of supercomputer memory positional effects in DRAM and SRAM faults. In SC ’13: Proceedings of the International Conference on High Performance Computing, Networking, Storage and Analysis. 1–11.
[34]
Steffen Buch, Micron Technology. 2020. Questions to Ask Your Memory Supplier… About Functional Safety for DRAM. https://www.youtube.com/watch?v=mzcbtXdWDcg, visited 2021-07-16.
[35]
Kyle Wiggers. 2019. Tesla claims its latest self-driving chip is 7 times more powerful than its rivals’. https://venturebeat.com/2019/04/22/tesla-claims-its-latest-self-driving-chip-is-six-times-more-powerful-than-its-rivals/, visited 2021-07-15.

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cover image ACM Other conferences
MEMSYS '21: Proceedings of the International Symposium on Memory Systems
September 2021
158 pages
ISBN:9781450385701
DOI:10.1145/3488423
Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Published: 09 May 2022

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Author Tags

  1. ASIL
  2. Automotive
  3. Component Fault Trees
  4. DRAM
  5. ECC
  6. Fault Tree Analysis
  7. LPDDR4
  8. Safety

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MEMSYS 2021
MEMSYS 2021: The International Symposium on Memory Systems
September 27 - 30, 2021
DC, Washington DC, USA

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