Article

Near-Optimal Precharging in High-Performance Nanoscale CMOS Caches

Authors:

Babak FalsafiAuthors Info & Claims

MICRO 36: Proceedings of the 36th annual IEEE/ACM International Symposium on Microarchitecture

Page 67

Published: 03 December 2003 Publication History

Abstract

High-performance caches statically pull up the bit-linesin all cache subarrays to optimize cache accesslatency. Unfortunately, such an architecture results in asignificant waste of energy in nanoscale CMOS implementationsdue to high leakage and bitline discharge inthe unaccessed subarrays. Recent research advocatesbitline isolation to control precharging of individualsubarrays using bitline precharge devices. In this paper,we carefully evaluate the energy and performancetrade-offs of bitline isolation, and propose a techniqueto exploit nearly its full potential to eliminate dischargeand reduce overall energy in level-one caches.Cycle-accurate and circuit simulation results of awide-issue superscalar processor indicate that: (1) infuture CMOS technologies (e.g., 70nm and beyond),cache architectures that exploit bitline isolation caneliminate up to 90% of the bitline discharge, (2) on-demandprecharging (i.e., decoding the address andsubsequently precharging the accessed subarrays) is notviable in level-one caches because prechargingincreases the cache access latency, and (3) our proposalfor gated precharging to exploit subarray referencelocality and precharging only the recently accessed sub-arrayseliminates nearly all of bitline discharge innanoscale CMOS caches with only a 1% of performancedegradation.

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Cited By

Chung SSkadron K(2008)On-Demand Solution to Minimize I-Cache Leakage Energy with Maintaining PerformanceIEEE Transactions on Computers10.1109/TC.2007.7077057:1(7-24)Online publication date: 1-Jan-2008
https://dl.acm.org/doi/10.1109/TC.2007.70770
Rao RWenck JFranklin DAmirtharajah RAkella V(2006)Segmented bitline cacheProceedings of the 13th international conference on High Performance Computing10.1007/11945918_17(123-134)Online publication date: 18-Dec-2006
https://dl.acm.org/doi/10.1007/11945918_17
Chung SSkadron K(2006)Using branch prediction information for near-optimal i-cache leakageProceedings of the 11th Asia-Pacific conference on Advances in Computer Systems Architecture10.1007/11859802_4(24-37)Online publication date: 6-Sep-2006
https://dl.acm.org/doi/10.1007/11859802_4
Show More Cited By

Index Terms

Near-Optimal Precharging in High-Performance Nanoscale CMOS Caches
1. Hardware

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cover image ACM Conferences

MICRO 36: Proceedings of the 36th annual IEEE/ACM International Symposium on Microarchitecture

December 2003

412 pages

ISBN:076952043X

Copyright © Copyright (c) 2003 Institute of Electrical and Electronics Engineers, Inc. All rights reserved.

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SIGMICRO: ACM Special Interest Group on Microarchitectural Research and Processing

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IEEE Computer Society

United States

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Published: 03 December 2003

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MICRO-36

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MICRO-36: The 36th Annual International Symposium on Microarchitecture

December 3 - 5, 2003

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MICRO 36 Paper Acceptance Rate 35 of 134 submissions, 26%;

Overall Acceptance Rate 484 of 2,242 submissions, 22%

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Cited By

Chung SSkadron K(2008)On-Demand Solution to Minimize I-Cache Leakage Energy with Maintaining PerformanceIEEE Transactions on Computers10.1109/TC.2007.7077057:1(7-24)Online publication date: 1-Jan-2008
https://dl.acm.org/doi/10.1109/TC.2007.70770
Rao RWenck JFranklin DAmirtharajah RAkella V(2006)Segmented bitline cacheProceedings of the 13th international conference on High Performance Computing10.1007/11945918_17(123-134)Online publication date: 18-Dec-2006
https://dl.acm.org/doi/10.1007/11945918_17
Chung SSkadron K(2006)Using branch prediction information for near-optimal i-cache leakageProceedings of the 11th Asia-Pacific conference on Advances in Computer Systems Architecture10.1007/11859802_4(24-37)Online publication date: 6-Sep-2006
https://dl.acm.org/doi/10.1007/11859802_4
Kim NFlautner KBlaauw DMudge TJoshi RChoi KTiwari VRoy K(2004)Single-vDD and single-vT super-drowsy techniques for low-leakage high-performance instruction cachesProceedings of the 2004 international symposium on Low power electronics and design10.1145/1013235.1013254(54-57)Online publication date: 9-Aug-2004
https://dl.acm.org/doi/10.1145/1013235.1013254

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