Article

Dynamic fine-grain leakage reduction using leakage-biased bitlines

Authors:

Krste AsanovićAuthors Info & Claims

ISCA '02: Proceedings of the 29th annual international symposium on Computer architecture

Pages 137 - 147

Published: 01 May 2002 Publication History

Abstract

Leakage power is dominated by critical paths, and hence dynamic deactivation of fast transistors can yield large savings. We introduce metrics for comparing fine-grain dynamic deactivation techniques that include the effects of deactivation energy and startup latencies, as well as long-term leakage current. We present a new circuit-level technique for leakage current reduction, leakage-biased bitlines, that has low deactivation energy and fast wakeup times. We show how this technique can be applied at a fine grain within an active microprocessor, and how microarchitectural scheduling policies can improve its performance. Using leakage-biased bitlines to deactivate SRAM read paths within I-cache memories saves over 24% of leakage energy and 22% of total I-cache energy when using a 70nm process. In the register file, fine-grained read port deactivation saves nearly 50% of leakage energy and 22% of total energy. Independently, turning off idle register file subbanks saves over 67% of leakage energy (57% total register file energy) with no loss in performance.

References

[1]

M. Allarm, M. H. Anis, and M. I. Elmasry. High-speed dynamic logic styles for scaled-down CMOS and MTCMOS technologies. In ISLPED, pages 155-160, 2000.

Digital Library

[2]

D. Burger and T. Austin. The SimpleScalar tool set, version 2.0. Technical Report CS-TR-97-1342, University Wisconsin, Madison, June 1997.

Digital Library

[3]

J. A. Butts and G. S. Sohi. A static power model for architects. In MICRO-33, pages 191-201, December 2000.

Digital Library

[4]

A. Chandrakasan, W. J. Bowhill, and F. Fox. Design of High Performance Microprocessor Circuits. IEEE Press, 2000.

Digital Library

[5]

V. De and S. Borkar. Technology and design challenges low power and high performance. In ISLPED, pages 163-168, 1999.

Digital Library

[6]

I.T.R. for Semiconductors. 2000 update, process integration, devices, and structures. Technical report, ITRS, 2000.

[7]

S. Geissler et al. A low-power RISC microprocessor using dual PLLs in a 0.13 µm SOI technology with copper interconnect and low-k BEOL dielectric. In ISSCC Digest, February 2002.

[8]

P. E. Gronowski et al. A 433-MHz 64-b quad-issue microprocessor. IEEE JSSC, 31(11):1687-1696, November 1996.

[9]

J. P. Halter and F. Najm. A gate-level leakage power reduction method for ultra-low-power CMOS circuis. In Custom Integrated Circuits Conf., pages 457-478, 1997.

[10]

F. Hamzaoglu et al. Dual-vt SRAM cells with full-swing single-ended bit line sensing for high-performance on-chip cache in 0.13 µm technology generation. In ISLPED, pages 15 - 19, 2000.

Digital Library

[11]

T. Inukai. Boosted-gate MOS (BGMOS): Device/circuit operation scheme to achieve leakage-free giga-scale integration. In Custom Integrated Circuits Conf., pages 409-412, 2000.

[12]

M. C. Johnson, D. Somasekhar, L.-Y. Chiou, and K. Roy. Leakage control with efficient use of transistor stacks in single threshold cmos. In IEEE Transactions on VLSI Systems, February 2002.

Digital Library

[13]

J. T. Kao and A. P. Chandrakasan. Dual-threshold voltage techniques for low-power digital circuits. IEEE JSSC, 35(7):1009-1018, July 2000.

[14]

S. Kaxiras, Z. Hu, and M. Martonosi. Cache decay: exploiting generational behavior to reduce cache leakage power. In ISCA 28, pages 240-251, May 2001.

Digital Library

[15]

A. Keshavarzi et al. Effectiveness of reverse body bias for leakage control in scaled dual Vt CMOS ICs. In ISLPED, pages 207-212, 2001.

Digital Library

[16]

S. V. Kosonocky et al. Enhanced multi-threshold (MTCMOS) circuits using variable well bias. In ISLPED, pages 165-169, 2001.

Digital Library

[17]

T. Kuroda et al. A 0.9-V, 150-MHz, 10-mW, 4 mm2, 2-D discrete cosine transform core processor with variable threshold-voltage (VT) scheme. IEEE JSSC, 31(11):1770-1779, November 1996.

[18]

T. Kuroda et al. Variable supply-voltage scheme for low-power high-speed CMOS digital design. IEEE JCCS, 33(3):454-462, March 1998.

[19]

W. Lee et al. A 1-V programmable DSP for wireless communications. IEEE JSSC, 32(11):1766-1776, November 1997.

[20]

H. Makino et al. An auto-backgate-controlled MT-CMOS circuit. In Symp. on VLSI Circuits, pages 42-43, 1998.

[21]

T. McPherson et al. 760MHz G6 S/390 microprocessor exploiting multiple Vt and copper interconnects. In ISSCC Digest, pages 96-97, 2000.

[22]

M. Miyazaki et al. A 1000-MIPS/W microprocessor using speed-adaptive threshold-voltage CMOS with forward bias. In ISSCC Digest, pages 420-421, 2000.

[23]

J. Montanaro et al. A 160-MHz, 32-b, 0.5-W CMOS RISC microprocessor. IEEE JSSC, 31(11):1703-1714, November 1996.

[24]

S. Mutoh et al. 1-V power supply high-speed digital circuit technology with multithreshold-voltage CMOS. IEEE JSSC, 30(8):847-854, August 1995.

[25]

S. Narendra et al. Scaling of stack effect and its application for leakage reduction. In ISLPED, pages 195-200, 2001.

Digital Library

[26]

M. Powell et al. Gated Vdd: A circuit technique to reduce leakage in deep-submicron cache memories. In ISLPED, 2000.

Digital Library

[27]

R. P. Preston et al. Design of an 8-wide superscalar RISC microprocessor with simultaneous multithreading. In ISSCC Digest and Visuals Supplement, February 2002.

[28]

K. Seta et al. 50% active-power saving without speed degradation using standby power reduction (SPR) circuit. In ISSCC Digest, pages 318-319, 1995.

[29]

S. Shigemasu et al. A 1-V high-speed MTCMOS circuit scheme for power-down application circuits. IEEE JSSC, 32(6):861-869, June 1997.

[30]

M. Takahasi et al. A 60-mw MPEG4 video codec using clustered voltage scaling with variable supply-voltage scheme. IEEE JSSC, 33(11):1772-1778, November 1998.

[31]

J. Tseng and K. Asanović. Energy-efficient register access. In Proc. of the 13th Symposium on Integrated Circuits Systems Design, Manaus, Brazil, September 2000.

Digital Library

[32]

K. Usami et al. Automated low-power technique exploting multiple supply voltages applied to a media processor. IEEE JSSC, 33(3):463-471, March 1998.

[33]

L. Villa, M. Zhang, and K. Asanović. Dynamic zero compression for cache energy reduction. In MICRO-33, 2000.

Digital Library

[34]

L. Wei et al. Design and optimization of low voltage high performance dual threshold CMOS circuits. In DAC, pages 489-494, 1998.

Digital Library

[35]

Y. Ye, S. Borkar, and V. De. A technique for standby leakage reduction in high-performance circuits. In Symp. on VLSI Circuits, pages 40-41, 1998.

[36]

W. Zhang et al. Exploiting VLIW schedule slacks for dynamic and leakage energy reduction. In MICRO-34, December 2001.

Digital Library

Cited By

Wen HZhang WChatha KErnst RRaghunathan AIyer R(2014)Reducing cache leakage energy for hybrid SPM-cache architecturesProceedings of the 2014 International Conference on Compilers, Architecture and Synthesis for Embedded Systems10.1145/2656106.2656124(1-9)Online publication date: 12-Oct-2014
https://dl.acm.org/doi/10.1145/2656106.2656124
Homayoun HSasan AGupta AVeidenbaum AKurdahi FDutt NAmato NFranke HKelly P(2010)Multiple sleep modes leakage control in peripheral circuits of a all major SRAM-based processor unitsProceedings of the 7th ACM international conference on Computing frontiers10.1145/1787275.1787339(297-308)Online publication date: 17-May-2010
https://dl.acm.org/doi/10.1145/1787275.1787339
Bollapalli KGarg RGulati KKhatri SLombardi FBhanja SMassoud YBahar R(2009)Low power and high performance sram design using bank-based selective forward body biasProceedings of the 19th ACM Great Lakes symposium on VLSI10.1145/1531542.1531643(441-444)Online publication date: 10-May-2009
https://dl.acm.org/doi/10.1145/1531542.1531643
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Index Terms

Dynamic fine-grain leakage reduction using leakage-biased bitlines
1. Hardware

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Information & Contributors

Information

Published In

cover image ACM Conferences

ISCA '02: Proceedings of the 29th annual international symposium on Computer architecture

May 2002

346 pages

ISBN:076951605X

Conference Chair:
Yale Patt
The University of Texas at Austin
,
Program Chair:
Dirk Grunwald
Univeristy of Colorado at Boulder
,
Publications Chair:
Kevin Skadron
University of Virginia

ACM SIGARCH Computer Architecture News Volume 30, Issue 2
Special Issue: Proceedings of the 29th annual international symposium on Computer architecture (ISCA '02)
May 2002
304 pages
ISSN:0163-5964
DOI:10.1145/545214
Issue’s Table of Contents

Copyright © Copyright (c) 2002 Institute of Electrical and Electronics Engineers, Inc. All rights reserved.

Sponsors

IEEE TCCA: IEEE Computer Society Technical Committee on Computer Architecture
SIGARCH: ACM Special Interest Group on Computer Architecture

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IEEE Computer Society

United States

Publication History

Published: 01 May 2002

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Dynamic Leakage Reduction

Qualifiers

Article

Conference

ISCA02

Sponsor:

IEEE TCCA
SIGARCH

ISCA02: 29th Annual International Symposium on Computer Architecture

May 25 - 29, 2002

Alaska, Anchorage

Acceptance Rates

ISCA '02 Paper Acceptance Rate 27 of 180 submissions, 15%;

Overall Acceptance Rate 543 of 3,203 submissions, 17%

Upcoming Conference

ISCA '25

Sponsor:
sigarch

The 52nd Annual International Symposium on Computer Architecture

June 21 - 25, 2025

Tokyo , Japan

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Cited By

Wen HZhang WChatha KErnst RRaghunathan AIyer R(2014)Reducing cache leakage energy for hybrid SPM-cache architecturesProceedings of the 2014 International Conference on Compilers, Architecture and Synthesis for Embedded Systems10.1145/2656106.2656124(1-9)Online publication date: 12-Oct-2014
https://dl.acm.org/doi/10.1145/2656106.2656124
Homayoun HSasan AGupta AVeidenbaum AKurdahi FDutt NAmato NFranke HKelly P(2010)Multiple sleep modes leakage control in peripheral circuits of a all major SRAM-based processor unitsProceedings of the 7th ACM international conference on Computing frontiers10.1145/1787275.1787339(297-308)Online publication date: 17-May-2010
https://dl.acm.org/doi/10.1145/1787275.1787339
Bollapalli KGarg RGulati KKhatri SLombardi FBhanja SMassoud YBahar R(2009)Low power and high performance sram design using bank-based selective forward body biasProceedings of the 19th ACM Great Lakes symposium on VLSI10.1145/1531542.1531643(441-444)Online publication date: 10-May-2009
https://dl.acm.org/doi/10.1145/1531542.1531643
Hunter HNystrom EConnors DHwu W(2009)Hardware-compiler co-design for adjustable data power savingsMicroprocessors & Microsystems10.1016/j.micpro.2009.02.00333:4(244-253)Online publication date: 1-Jun-2009
https://dl.acm.org/doi/10.1016/j.micpro.2009.02.003
Amelifard BFallah FPedram M(2008)Leakage minimization of SRAM cells in a dual-V t and Dual-T ox technologyIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2008.200045916:7(851-860)Online publication date: 1-Jul-2008
https://dl.acm.org/doi/10.1109/TVLSI.2008.2000459
Gonzalez IGalluzzi MVeidenbaum ARamirez MCristal AValero M(2008)A distributed processor state management architecture for large-window processorsProceedings of the 41st annual IEEE/ACM International Symposium on Microarchitecture10.1109/MICRO.2008.4771775(11-22)Online publication date: 8-Nov-2008
https://dl.acm.org/doi/10.1109/MICRO.2008.4771775
Tanaka KFujita T(2007)Leakage energy reduction in cache memory by software self-invalidationProceedings of the 12th Asia-Pacific conference on Advances in Computer Systems Architecture10.5555/2392163.2392180(163-174)Online publication date: 23-Aug-2007
https://dl.acm.org/doi/10.5555/2392163.2392180
Tanaka KKawahara T(2007)Leakage energy reduction in cache memory by data compressionACM SIGARCH Computer Architecture News10.1145/1360464.136047235:5(17-24)Online publication date: 1-Dec-2007
https://dl.acm.org/doi/10.1145/1360464.1360472
Zhang WAllu B(2007)Reducing branch predictor leakage energy by exploiting loopsACM Transactions on Embedded Computing Systems10.1145/1234675.12346786:2(11-es)Online publication date: 1-May-2007
https://dl.acm.org/doi/10.1145/1234675.1234678
Zhang W(2006)Compiler-guided next sub-bank prediction for reducing instruction cache leakage energyJournal of Embedded Computing10.5555/1370986.13709902:1(35-48)Online publication date: 1-Jan-2006
https://dl.acm.org/doi/10.5555/1370986.1370990
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