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A multiple stream microprocessor prototype system: AMP-1

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Edward S. DavidsonAuthors Info & Claims

ISCA '80: Proceedings of the 7th annual symposium on Computer Architecture

Pages 9 - 16

https://doi.org/10.1145/800053.801903

Published: 06 May 1980 Publication History

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Abstract

A general-purpose multiple-stream processor with shared memory and a single time-multiplexed synchronous bus has been implemented. The AMP-1 system uses eight standard microprocessors and 64K bytes of memory. The design is highly efficient in the use of processor, bus, and memory resources. Preliminary performance measurements agree closely with an analytic memory access conflict model and show extremely low conflict-based performance degradation. Heavy interleaving of the memory and effective multitasking of a job can yield significant performance speedups. Considerations for future implementations are presented.

References

[1]

S. M. Thatte and J. A. Abraham, "Test Generation for General Microprocessor Architectures," Proc. 9th International Symposium on Fault-Tolerant Computing, Madison, Wisconsin, June 20-22, 1979, pp. 203-210.

Google Scholar

[2]

J. A. Abraham and G. Metze, "Roving Diagnosis for High Performance Digital Systems," Proc. 1978 Conf. on Information Sciences and Systems, The Johns Hopkins University, Baltimore, Maryland, March 29-31, 1978, pp. 221-226.

Google Scholar

[3]

F. A. Briggs and E. S. Davidson, "Organization of Semiconductor Memories for Parallel-Pipelined Processors," IEEE-TC, Feb. 1977, pp. 162-169

Google Scholar

[4]

J. Emer, "Shared Resources for Multiple Instruction Stream Pipelined Processors," Coordinated Science Laboratory Report R-838, March 1979.

Google Scholar

[5]

W. J. Kaminsky and E. S. Davidson, "Developing a Multiple Stream Single Chip Processor," Computer, Dec. 1979, pp. 66-76.

Google Scholar

[6]

W. J. Kaminsky, "Architecture for Multiple Instruction Stream LSI Processors," Coordinated Science Laboratory Report R-796, Oct. 1977.

Google Scholar

[7]

J. S. Emer and E. S. Davidson, "Control Store Organization for Multiple Stream Pipelined Processors," Proc. 1978 Int'l Conf. on Parallel Processing, pp. 43-48.

Google Scholar

[8]

E. S. Davidson, L. E. Shar, A. T. Thomas, and J. H. Patel, "Effective Control for Pipelined Computers," Proc. Compcon Spring, 1975, pp. 181-184.

Google Scholar

[9]

R. J. Swan, S. H. Fuller, and D. P. Siewiorek, "Cm*-A modular, multimicroprocessor," Proc. NCC, 1977, pp. 637-644.

Digital Library

Google Scholar

[10]

R. L. Budzinski, "Dynamic Memory Allocation for a Virtual Memory Computer," Coordinated Science Laboratory Report R-754, Jan. 1977

Google Scholar

[11]

D. W. Hammerstrom and E. S. Davidson, "Information Content of CPU Memory Referencing Behavior," 4th Annual Symposium on Computer Architecture, 1977, pp. 184-192.

Digital Library

Google Scholar

[12]

D. W. Hammerstrom, "Analysis of Memory Addressing Architecture," Coordinated Science Laboratory Report R-777, July 1977.

Google Scholar

[13]

W. Abu-Sufah, "Improving the Performance of Virtual Memory Computers," Department of Computer Science Report R-78-945, University of Illinois, Nov. 1978.

Google Scholar

Cited By

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Patel J(1998)Retrospective: a low-overhead coherence solution for multiprocessors with private cache memories25 years of the international symposia on Computer architecture (selected papers)10.1145/285930.285947(39-41)Online publication date: 1-Aug-1998
https://dl.acm.org/doi/10.1145/285930.285947
Agarwal A(1992)Performance Tradeoffs in Multithreaded ProcessorsIEEE Transactions on Parallel and Distributed Systems10.1109/71.1590373:5(525-539)Online publication date: 1-Sep-1992
https://dl.acm.org/doi/10.1109/71.159037
Arango MBadr HGelernter D(1985)Staged Circuit SwitchingIEEE Transactions on Computers10.1109/TC.1985.167655534:2(174-180)Online publication date: 1-Feb-1985
https://dl.acm.org/doi/10.1109/TC.1985.1676555
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A multiple stream microprocessor prototype system: AMP-1

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Published In

ISCA '80: Proceedings of the 7th annual symposium on Computer Architecture

May 1980

333 pages

ISBN:9781450373906

DOI:10.1145/800053

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Association for Computing Machinery

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Published: 06 May 1980

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Cited By

View all

Patel J(1998)Retrospective: a low-overhead coherence solution for multiprocessors with private cache memories25 years of the international symposia on Computer architecture (selected papers)10.1145/285930.285947(39-41)Online publication date: 1-Aug-1998
https://dl.acm.org/doi/10.1145/285930.285947
Agarwal A(1992)Performance Tradeoffs in Multithreaded ProcessorsIEEE Transactions on Parallel and Distributed Systems10.1109/71.1590373:5(525-539)Online publication date: 1-Sep-1992
https://dl.acm.org/doi/10.1109/71.159037
Arango MBadr HGelernter D(1985)Staged Circuit SwitchingIEEE Transactions on Computers10.1109/TC.1985.167655534:2(174-180)Online publication date: 1-Feb-1985
https://dl.acm.org/doi/10.1109/TC.1985.1676555
Arango MGelernter DBadr HBernstein AWood DLam S(1983)Staged circuit switching for network computersProceedings of the symposium on Communications Architectures & Protocols10.1145/1035237.1035259(94-100)Online publication date: 8-Oct-1983
https://dl.acm.org/doi/10.1145/1035237.1035259
Arango MGelernter DBadr HBernstein A(1983)Staged circuit switching for network computersACM SIGCOMM Computer Communication Review10.1145/1024840.103525913:2(94-100)Online publication date: 1-Apr-1983
https://dl.acm.org/doi/10.1145/1024840.1035259
Tartar JBradshaw CSherman G(1980)Multiprocessor hardwareProceedings of the ACM 1980 annual conference10.1145/800176.810010(518-526)Online publication date: 1-Jan-1980
https://dl.acm.org/doi/10.1145/800176.810010

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The PowerPC 620 microprocessor: a high performance superscalar RISC microprocessor

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