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Buffer insertion with adaptive blockage avoidance

Published: 07 April 2002 Publication History

Abstract

Buffer insertion is a fundamental technology for VLSI interconnect optimization. Several existing buffer insertion algorithms have evolved from van Ginneken's classic algorithm. In this work, we extend van Ginneken's algorithm to handle blockages in the layout. Given a Steiner tree containing a Steiner point that overlaps a blockage, a local adjustment is made to the tree topology that enables additional buffer insertion candidates to be considered. This adjustment is adaptive to the demand on buffer insertion and is incurred only when it facilitates the maximal slack solution. This approach can be combined with any performance-driven Steiner tree construction. The overall time complexity has linear dependence on the number of blockages and quadratic dependence on the number of potential buffer locations. Experiments on several large nets confirm that high-quality solutions can be obtained through this technique with little CPU cost.

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  • (2013)Depth controlled symmetric function fanin tree restructureProceedings of the International Conference on Computer-Aided Design10.5555/2561828.2561945(585-591)Online publication date: 18-Nov-2013
  • (2010)Algorithm engineeringundefinedOnline publication date: 1-Jan-2010
  • (2005)Buffered tree refinement considering timing and congestion2005 IEEE VLSI-TSA International Symposium on VLSI Design, Automation and Test, 2005. (VLSI-TSA-DAT).10.1109/VDAT.2005.1500021(63-66)Online publication date: 2005
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    cover image ACM Conferences
    ISPD '02: Proceedings of the 2002 international symposium on Physical design
    April 2002
    216 pages
    ISBN:1581134606
    DOI:10.1145/505388
    Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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    Publication History

    Published: 07 April 2002

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    April 7 - 10, 2002
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    Cited By

    View all
    • (2013)Depth controlled symmetric function fanin tree restructureProceedings of the International Conference on Computer-Aided Design10.5555/2561828.2561945(585-591)Online publication date: 18-Nov-2013
    • (2010)Algorithm engineeringundefinedOnline publication date: 1-Jan-2010
    • (2005)Buffered tree refinement considering timing and congestion2005 IEEE VLSI-TSA International Symposium on VLSI Design, Automation and Test, 2005. (VLSI-TSA-DAT).10.1109/VDAT.2005.1500021(63-66)Online publication date: 2005
    • (2004)An efficient routing tree construction algorithm with buffer insertion, wire sizing and obstacle considerationsProceedings of the 2004 Asia and South Pacific Design Automation Conference10.5555/1015090.1015181(361-366)Online publication date: 27-Jan-2004
    • (2004)A place and route aware buffered Steiner tree constructionProceedings of the 2004 Asia and South Pacific Design Automation Conference10.5555/1015090.1015180(355-360)Online publication date: 27-Jan-2004
    • (2004)Accurate estimation of global buffer delay within a floorplanProceedings of the 2004 IEEE/ACM International conference on Computer-aided design10.1109/ICCAD.2004.1382667(706-711)Online publication date: 7-Nov-2004
    • (2003)Porosity aware buffered steiner tree constructionProceedings of the 2003 international symposium on Physical design10.1145/640000.640035(158-165)Online publication date: 6-Apr-2003

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