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Buffer insertion with adaptive blockage avoidance

Published: 01 November 2006 Publication History

Abstract

Buffer insertion is a fundamental technology for very large scale integration interconnect optimization. This work presents the repeater insertion with adaptive tree adjustment (RIATA) heuristic that directly extends van Ginneken's classic algorithm to handle blockages in the layout. Given a Steiner tree containing a Steiner point that overlaps a blockage, a local adjustment is made to the tree topology that enables additional buffer insertion candidates to be considered. This adjustment adapts to the demand on buffer insertion and is incurred only when it facilitates the maximal slack solution. RIATA can be combined with any performance-driven Steiner tree algorithm and permits various solution search schemes to achieve different solution quality and runtime tradeoffs. Experiments on several large nets confirms that high-quality solutions can be obtained through this technique with greater efficiency than simultaneous approaches.

Cited By

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  • (2013)Embedding repeaters in silicon IPs for cross-IP interconnectionsIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2012.219043421:3(597-601)Online publication date: 1-Mar-2013
  • (2012)Reclaiming over-the-IP-block routing resources with buffering-aware rectilinear Steiner minimum tree constructionProceedings of the International Conference on Computer-Aided Design10.1145/2429384.2429410(137-143)Online publication date: 5-Nov-2012
  • (2010)Minimizing clock latency range in robust clock tree synthesisProceedings of the 2010 Asia and South Pacific Design Automation Conference10.5555/1899721.1899817(389-394)Online publication date: 18-Jan-2010
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cover image IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems  Volume 22, Issue 4
November 2006
127 pages

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IEEE Press

Publication History

Published: 01 November 2006

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Cited By

View all
  • (2013)Embedding repeaters in silicon IPs for cross-IP interconnectionsIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2012.219043421:3(597-601)Online publication date: 1-Mar-2013
  • (2012)Reclaiming over-the-IP-block routing resources with buffering-aware rectilinear Steiner minimum tree constructionProceedings of the International Conference on Computer-Aided Design10.1145/2429384.2429410(137-143)Online publication date: 5-Nov-2012
  • (2010)Minimizing clock latency range in robust clock tree synthesisProceedings of the 2010 Asia and South Pacific Design Automation Conference10.5555/1899721.1899817(389-394)Online publication date: 18-Jan-2010
  • (2007)Fast dual-vdd buffering based on interconnect prediction and samplingProceedings of the 2007 international workshop on System level interconnect prediction10.1145/1231956.1231976(95-102)Online publication date: 17-Mar-2007
  • (2007)Utilizing redundancy for timing critical interconnectIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2007.90391115:10(1067-1080)Online publication date: 1-Oct-2007
  • (2005)Making fast buffer insertion even faster via approximation techniquesProceedings of the 2005 Asia and South Pacific Design Automation Conference10.1145/1120725.1120733(13-18)Online publication date: 18-Jan-2005
  • (2005)Power optimal dual-Vdd buffered tree considering buffer stations and blockagesProceedings of the 42nd annual Design Automation Conference10.1145/1065579.1065709(497-502)Online publication date: 13-Jun-2005
  • (2004)Complexity analysis and speedup techniques for optimal buffer insertion with minimum costProceedings of the 2004 Asia and South Pacific Design Automation Conference10.5555/1015090.1015257(609-614)Online publication date: 27-Jan-2004

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