Nothing Special   »   [go: up one dir, main page]

skip to main content
10.1145/505388.505400acmconferencesArticle/Chapter ViewAbstractPublication PagesispdConference Proceedingsconference-collections
Article

Routability driven white space allocation for fixed-die standard-cell placement

Published: 07 April 2002 Publication History

Abstract

The use of white space in fixed-die standard-cell placement is an effective way to improve routability. In this paper, we present a white space allocation approach that dynamically assigns white space according to the congestion distribution of the placement. In the top-down placement flow, white space is assigned to congested regions using a smooth allocating function. A post allocation optimization step is taken to further improve placement quality. Experimental results show that the proposed allocation approach, combined with a multilevel placement flow, significantly improves placement routability and layout quality.In our experiments, we compared our placement tool with two other fixed-die placers using an industrial place and route flow. Placements created by all three tools have been routed with an industrial router (Warp Route of Cadence). Compared with a leading-edge industrial tool, our placer produces placements with similar or better routability and on average 8.8% shorter routed wirelength. Furthermore, our tool produces placement that runs faster through the Warp Route compared with the industrial tool. Compared with a state-of-the-art academic placement tool (Capo/MetaPlacer), our placer shows ability to produce more routable placements: for 15 out of all 16 benchmarks our placer's outputs are routable while Capo/MetaPlacer only creates 4 routable placements.

References

[1]
M. A. Breuer. "A Class of Min-cut Placement Algorithms". In Design Automation Conference, pages 284--290. IEEE/ACM, 1977.
[2]
C. Sechen and A. Sangiovanni-Vincentelli. "TimberWolf3.2: A New Standard Cell Placement and Global Routing Package". In Design Automation Conference, pages 432--439. IEEE/ACM, 1986.
[3]
J. M. Kleinhans, G. Sigl, F. M. Johannes, and K. J. Antreich. "GORDIAN: VLSI Placement by Quadratic Programming and Slicing Optimization". IEEE Transactions on Computer Aided Design, 10(3):365--365, 1991.
[4]
S. Mayrhofer and U. Lauther. "Congestion-Driven Placement Using a New Multi-partitioning Heuristic". In International Conference on Computer-Aided Design, pages 332--335. IEEE, 1990.
[5]
C. E. Cheng. "RISA: Accurate and Efficient Placement Routability Modeling". In International Conference on Computer-Aided Design, pages 690--695, 1994.
[6]
M. Wang, X. Yang, and M. Sarrafzadeh. "Congestion Minimization During Placement". IEEE Transactions on Computer Aided Design, 19(10):1140--1148, 2000.
[7]
A. E. Caldwell, A. B. Kahng, and I. L. Markov. "Can Recursive Bisection Alone Produce Routable Placements?". In Design Automation Conference, pages 477--482. IEEE/ACM, June 2000.
[8]
P. N. Parakh, R. B. Brown, and K. A. Sakallah. "Congestion Driven Quadratic Placement". In Design Automation Conference, pages 275--278. IEEE/ACM, June 1998.
[9]
M. Sarrafzadeh and M. Wang. "NRG: Global and Detailed Placement". In International Conference on Computer-Aided Design. IEEE, November 1997.
[10]
M. Wang, X. Yang, and M. Sarrafzadeh. "Dragon2000: Fast Standard-cell Placement for Large Circuits". In International Conference on Computer-Aided Design, pages 260--263. IEEE, 2000.
[11]
X. Yang, R. Kastner, and M. Sarrafzadeh. "Congestion Reduction During Placement Based on Integer Programming". In International Conference on Computer-Aided Design, pages 573--576. IEEE, 2001.
[12]
J. Lou, S. Krishnamoorthy, and H. S. Sheng. "Estimating Routing Congestion using Probabilistic Analysis". In International Symposium on Physical Design, pages 112--117. ACM, April 2001.
[13]
X. Yang, R. Kastner, and M. Sarrafzadeh. "Congestion Estimation During Top-down Placement". In International Symposium on Physical Design, pages 164--169. ACM, April 2001.
[14]
G. Karypis, R. Aggarwal, V. Kumar, and S. Shekhar. "Multilevel Hypergraph Partitioning: Application in VLSI Domain". In Design Automation Conference, pages 526--529. IEEE/ACM, 1997.
[15]
NuCAD. "IBM-PLACE benchmark". http://www.ece.nwu.edu/nucad/ibm-place.html.

Cited By

View all
  • (2023)Estimating feature importance in circuit network using machine learningMultimedia Tools and Applications10.1007/s11042-023-16814-8Online publication date: 15-Sep-2023
  • (2017)Bacterial Foraging Optimization for VLSI Fragments PlacementProceedings of the Second International Scientific Conference “Intelligent Information Technologies for Industry” (IITI’17)10.1007/978-3-319-68321-8_35(341-348)Online publication date: 30-Sep-2017
  • (2016)Artificial Bee Colony Algorithm—A Novel Tool for VLSI PlacementProceedings of the First International Scientific Conference “Intelligent Information Technologies for Industry” (IITI’16)10.1007/978-3-319-33609-1_39(433-442)Online publication date: 24-Apr-2016
  • Show More Cited By

Index Terms

  1. Routability driven white space allocation for fixed-die standard-cell placement

    Recommendations

    Comments

    Please enable JavaScript to view thecomments powered by Disqus.

    Information & Contributors

    Information

    Published In

    cover image ACM Conferences
    ISPD '02: Proceedings of the 2002 international symposium on Physical design
    April 2002
    216 pages
    ISBN:1581134606
    DOI:10.1145/505388
    Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

    Sponsors

    Publisher

    Association for Computing Machinery

    New York, NY, United States

    Publication History

    Published: 07 April 2002

    Permissions

    Request permissions for this article.

    Check for updates

    Author Tags

    1. physical design
    2. placement
    3. routability

    Qualifiers

    • Article

    Conference

    ISPD02
    Sponsor:
    ISPD02: International Symposium on Physical Design
    April 7 - 10, 2002
    CA, San Diego, USA

    Acceptance Rates

    Overall Acceptance Rate 62 of 172 submissions, 36%

    Upcoming Conference

    ISPD '25
    International Symposium on Physical Design
    March 16 - 19, 2025
    Austin , TX , USA

    Contributors

    Other Metrics

    Bibliometrics & Citations

    Bibliometrics

    Article Metrics

    • Downloads (Last 12 months)13
    • Downloads (Last 6 weeks)2
    Reflects downloads up to 17 Nov 2024

    Other Metrics

    Citations

    Cited By

    View all
    • (2023)Estimating feature importance in circuit network using machine learningMultimedia Tools and Applications10.1007/s11042-023-16814-8Online publication date: 15-Sep-2023
    • (2017)Bacterial Foraging Optimization for VLSI Fragments PlacementProceedings of the Second International Scientific Conference “Intelligent Information Technologies for Industry” (IITI’17)10.1007/978-3-319-68321-8_35(341-348)Online publication date: 30-Sep-2017
    • (2016)Artificial Bee Colony Algorithm—A Novel Tool for VLSI PlacementProceedings of the First International Scientific Conference “Intelligent Information Technologies for Industry” (IITI’16)10.1007/978-3-319-33609-1_39(433-442)Online publication date: 24-Apr-2016
    • (2014)NTUplace4h: A Novel Routability-Driven Placement Algorithm for Hierarchical Mixed-Size Circuit DesignsIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2014.236045333:12(1914-1927)Online publication date: Dec-2014
    • (2013)Routability-driven placement for hierarchical mixed-size circuit designsProceedings of the 50th Annual Design Automation Conference10.1145/2463209.2488921(1-6)Online publication date: 29-May-2013
    • (2011)Routability-driven analytical placement for mixed-size circuit designsProceedings of the International Conference on Computer-Aided Design10.5555/2132325.2132348(80-84)Online publication date: 7-Nov-2011
    • (2011)Routability-driven analytical placement for mixed-size circuit designsProceedings of the 2011 IEEE/ACM International Conference on Computer-Aided Design10.1109/ICCAD.2011.6105309(80-84)Online publication date: 7-Nov-2011
    • (2009)GRPlacerProceedings of the 2009 International Conference on Computer-Aided Design10.1145/1687399.1687466(351-356)Online publication date: 2-Nov-2009
    • (2009)PlacementElectronic Design Automation10.1016/B978-0-12-374364-0.50018-7(635-685)Online publication date: 2009
    • (2009)Electronic Design AutomationundefinedOnline publication date: 11-Mar-2009
    • Show More Cited By

    View Options

    Login options

    View options

    PDF

    View or Download as a PDF file.

    PDF

    eReader

    View online with eReader.

    eReader

    Media

    Figures

    Other

    Tables

    Share

    Share

    Share this Publication link

    Share on social media