survey

Multi-core Devices for Safety-critical Systems: A Survey

Authors:

Jon Perez Cerrolaza,

Roman Obermaisser,

Francisco J. Cazorla,

Hamidreza Ahmadian,

Imanol AllendeAuthors Info & Claims

ACM Computing Surveys (CSUR), Volume 53, Issue 4

Article No.: 79, Pages 1 - 38

https://doi.org/10.1145/3398665

Published: 03 August 2020 Publication History

Abstract

Multi-core devices are envisioned to support the development of next-generation safety-critical systems, enabling the on-chip integration of functions of different criticality. This integration provides multiple system-level potential benefits such as cost, size, power, and weight reduction. However, safety certification becomes a challenge and several fundamental safety technical requirements must be addressed, such as temporal and spatial independence, reliability, and diagnostic coverage. This survey provides a categorization and overview at different device abstraction levels (nanoscale, component, and device) of selected key research contributions that support the compliance with these fundamental safety requirements.

References

[1]

Xavier Jean, Marc Gatti, Guy Berthon, and Marc Fumey. 2012. MULCORS-Use of Multicore Processors in Airborne Systems (EASA Project. 2011/6). Technical Report. EASA. Retrieved from https://www.easa.europa.eu/sites/default/files/dfu/CCC_12_006898-REV07%20-%20MULCORS%20Final%20Report.pdf.

[2]

WSTS. 2018. World semiconductor trade statistics (WSTS). Retrieved from https://www.wsts.org/.

[3]

Intel. 2020. Case Study, Intel Core 2 Duo Processor on KUKA Robot Controller. Retrieved from https://www.intel.com/content/dam/doc/case-study/industrial-core-kuka-study.pdf.

[4]

J. Abella and F. J. Cazorla. 2017. Chapter 9-Harsh computing in the space domain. In Rugged Embedded Syst., Augusto Vega, Pradip Bose, and Alper Buyuktosunoglu (Eds.). Morgan Kaufmann, Boston, 267--293.

[5]

J. Abella, F. J. Cazorla, E. Quiñones, A. Grasset, S. Yehia, P. Bonnot, D. Gizopoulos, R. Mariani, and G. Bernat. 2011. Towards improved survivability in safety-critical systems. In Proceedings of the IEEE 17th International On-Line Testing Symposium (IOLTS’11). 240--245.

[6]

J. Abella, C. Hernandez, E. Quiñones, F. J. Cazorla, P. R. Commy, M. Azkarate-Askasua, J. Perez, E. Mezzetti, and T. Vardanega. 2015. WCET analysis methods: Pitfalls and challenges on their trustworthiness. In Proceedings of the 10th IEEE International Symposium on Industrial Embedded Systems (SIES’15).

[7]

A. Agarwal, L. Bao, J. Brownet al. 2007. The tile processor (TM) architecture: Embedded multicore for networking and digital multimedia. In Proceedings of the 19th IEEE Hot Chips Symposium (HCS’07). 1--12.

[8]

I. Agirre, J. Abella, M. Azkarate-Askasua, and F. J. Cazorla. 2017. On the tailoring of CAST-32A certification guidance to real COTS multicore architectures. In Proceedings of the 12th IEEE International Symposium on Industrial Embedded Systems (SIES’17). 1--8.

[9]

I. Agirre, M. Azkarate-Askasua, A. Larrucea, J. Perez, T. Vardanega, and F. J. Cazorla. 2015. A safety concept for a railway mixed-criticality embedded system based on multicore partitioning. In Proceedings of the IEEE International Conference on Computers and Information Technology; Ubiquitous Computer and Communication; Dependable, Autonomic and Secure Computing; Pervasive Intelligence and Computing (CIT/IUCC/DASC/PICom’15). 1780--1787.

[10]

I. Agirre, M. Azkarate-askasua, A. Larrucea, J. Perez, T. Vardanega, and F. J. Cazorla. 2016. Automotive safety concept definition for mixed-criticality integration on a COTS multicore. In Computer Safety, Reliability, and Security, A. Skavhaug, J. Guiochet, E. Schoitsch, and F. Bitsch (Eds.). Springer, 273--285.

[11]

A. Agrawal, G. Fohler, J. Freitag, J. Nowotsch, S. Uhrig, and M. Paulitsch. 2017. Contention-aware dynamic memory bandwidth isolation with predictability in COTS multicores: An avionics case study. In Proceedings of the 29th Euromicro Conference on Real-Time Systems (ECRTS’17).

[12]

H. Ahmadian, R. Obermaisser, and J. Perez. 2018. Distributed Real-Time Architecture for Mixed-Criticality Systems. CRC Press, Taylor 8 Francis Incorporated.

[13]

M. A. Alam, K. Roy, and C. Augustine. 2011. Reliability and process-variation aware design of integrated circuits—A broader perspective. In Proceedings of the International Reliability Physics Symposium 4A.1.1–4A.1.11.

[14]

S. Alcaide, L. Kosmidis, C. Hernandez, and J. Abella. 2019. High-integrity GPU designs for critical real-time automotive systems. In Proceedings of the Conference on Design, Automation 8 Test (DATE’19). 824--829.

[15]

I. Allende, N. Mc Guire, J. Perez, L. G. Monsalve, N. Uriarte, and Obermaisser R.2019. Towards Linux for the development of mixed-criticality embedded systems based on multi-core devices. In Proceedings of the 15th European Dependable Computing Conference (EDCC’19). 47--54.

[16]

B. Anuradha and C. Vivekanandan. 2012. Usage of scratchpad memory in embedded systems—State of art. In Proceedings of the 3rd International Conference on Computing, Communication, and Networking Technologies (ICCCNT’12). 1--5.

[17]

J. Athavale, R. Mariani, and M. Paulitsch. 2019. Flight safety certification implications for complex multi-core processor based avionics systems. In Proceedings of the IEEE 25th International Symposium on On-Line Testing and Robust Syst. Design (IOLTS’19). 38--39.

[18]

A. Avižienis, J. C. Laprie, B. Randell, and C. Landwehr. 2004. Basic concepts and taxonomy of dependable and secure computing. In IEEE Transactions on Dependable and Secure Computing, Vol. 1. 11--33.

Digital Library

[19]

A. Barros and L. M. Pinho. 2011. Software transactional memory as a building block for parallel embedded real-time systems. In Proceedings of the 37th Euromicro Conference on Software Engineering and Advanced Applications (SEAA). 251--255.

[20]

H. Bauer, M. Patel, N. Santhanam, and B. Wiseman. 2015. McKinsey on Semiconductors. Technical Report.

[21]

C. Belwal and A. M. K. Cheng. 2011. Lazy versus eager conflict detection in software transactional memory: A real-time schedulability perspective. IEEE Embed. Syst. Lett. 3, 1 (2011), 37--41.

Digital Library

[22]

Pedro Benedicte, Carles Hernandez, Jaume Abella, and Francisco J. Cazorla. 2018. HWP: Hardware support to reconcile cache energy, complexity, performance and WCET estimates in multicore real-time systems. In Proceedings of the 30th Euromicro Conference on Real-Time Systems (ECRTS’18). 3:1–3:22.

[23]

S. Bensalem, K. Goossens, C. M. Kirsch, R. Obermaisser, E. A. Lee, and J. Sifakis. 2011. Time-predictable and composable architectures for dependable embedded systems. In Proceedings of the 9th ACM International Conference on Embedded Software (EMSOFT’11). 351--352.

[24]

C. Bernardeschi, L. Cassano, and A. Domenici. 2015. SRAM-based FPGA systems for safety-critical applications: A survey on design standards and proposed methodologies. J. Comput. Sci. Technol. 30, 2 (2015), 373--390.

[25]

A. Bilbao, I. Yarza, J. L. Montero, M. Azkarate-askasua, and N. Gonzalez. 2017. A railway safety and security concept for low-power mixed-criticality systems. In Proceedings of the IEEE 15th International Conference on Industrial Informatics (INDIN). 59--64.

[26]

J. Bin. 2014. Controlling Execution Time Variability Using COTS for Safety Critical Systems. Thesis, Université Paris-Sud.

[27]

J. Bin, S. Girbal, D. Gracia Pérez, A. Grasset, and A. Merigot. 2014. Studying co-running avionic real-time applications on multi-core COTS architectures. In Proceedings of the Embedded Real Time Software and Systems Conference

[28]

G. Blake, R. G. Dreslinski, and T. Mudge. 2009. A survey of multicore processors. IEEE Signal Process. Mag. 26, 6 (2009), 26--37.

[29]

C. Bolchini, M. K. Michael, A. Miele, and S. Neophytou. 2018. Dependability Threats. Springer.

[30]

E. Bolotin, I. Cidon, R. Ginosar, and A. Kolodny. 2004. QNoC: QoS architecture and design process for network on chip. J. Syst. Archit. 50, 2-3 (2004), 105--128.

Digital Library

[31]

C. Bradatsch, F. Kluge, and T. Ungerer. 2013. A cross-domain system architecture for embedded hard real-time many-core systems. In Proceedings of the IEEE 10th International Conference on High Performance Computing and Communications (HPCC’13). 2034--2041.

[32]

D. Bui, E. Lee, I. Liu, H. Patel, and J. Reineke. 2011. Temporal isolation on multiprocessing architectures. In Proceedings of the 48th ACM/EDAC/IEEE Design Automation Conference (DAC). 274--279.

[33]

A. Burns and R. I. David. 2018. A survey of research into mixed criticality systems. ACM Comput. Surv. 50, 6 (2018).

[34]

A. Burns, J. Harbin, and L.S. Indrusiak. 2014. A wormhole NoC protocol for mixed criticality systems. In Proceedings of the IEEE Real-Time Syst. Symposium (RTSS’14). 184--195.

[35]

D. Buttle. 2012. Real-Time in the Prime-Time—ECRTS Keynote Talk. Technical Report. ETAS Gmbh.

[36]

CAST. 2016. Multi-core Processors—Position Paper CAST-32A. Technical Report.

[37]

F. J. Cazorla, J. Abella, J. Andersson, T. Vardanega, F. Vatrinet, I. Bate, I. Broster, M. Azkarate-Askasua, F. Wartel, L. Cucu, F. Cros, G. Farrall, A. Gogonel, A. Gianarro, B. Triquet, C. Hernandez, C. Lo, C. Maxim, D. Morales, E. Quinones, E. Mezzetti, L. Kosmidis, I. Aguirre, M. Fernandez, M. Slijepcevic, P. Conmy, and W. Talaboulma. 2016. PROXIMA: Improving measurement-based timing analysis through randomisation and probabilistic analysis. In Proceedings of the Euromicro Conference on Digital Systems Design (DSD’16). 276--285.

[38]

F. J. Cazorla, L. Kosmidis, E. Mezzetti, C. Hernandez, J. Abella, and T. Vardanega. 2019. Probabilistic worst-case timing analysis: Taxonomy and comprehensive survey. ACM Comput. Surv. 52, 1 (2019).

[39]

S. Chakraborty and S. Ramesh. 2015. Guest editorial special section on automotive embedded systems and software. IEEE Trans. Comput.-Aided Design Integr. Circ. Syst. 34, 11 (2015), 1701--1703.

Digital Library

[40]

Jason A. Cheatham, John M. Emmert, and Stan Baumgart. 2006. A survey of fault tolerant methodologies for FPGAs. ACM Trans. Des. Autom. Electron. Syst. 11, 2 (2006), 501--533.

Digital Library

[41]

G. Corradi. 2017. Tools, architectures and trends on industrial all programmable heterogeneous MPSoC (KeyNote). In Proceedings of the 29th Euromicro Conference on Real-Time Systems (ECRTS’17).

[42]

A. Crespo, P. Balbastre, K. Chappuis, J. Coronel, J. Fanguède, P. Lucas, and J. Perez. 2018. Execution Environment. CRC Press.

[43]

A. Crespo, P. Balbastre, J. Sim, J. Coronel, D. Gracia Perez, and P. Bonnot. 2018. Hypervisor-based multicore feedback control of mixed-criticality systems. IEEE Access 6 (2018), 50627--50640.

[44]

N. Dagieu, A. Spyridakis, and D. Raho. 2016. Memguard: A memory bandwith management in mixed criticality virtualized systems memguard KVM scheduling. In Proceedings of the 10th International Conference on Mobile Ubiquitous Computing, Systems, Services, and Technologies (UBICOMM’16). Retrieved from https://www.thinkmind.org/index.php?view=article8articleid=ubicomm_2016_1_40_10072.

[45]

Shidhartha Das. 2009. Razor: A Variability-tolerant Design Methodology for Low-power and Robust Computing. Thesis, The University of Michigan.

[46]

S. Das. 2018. Variation-Mitigation for Reliable, Dependable and Energy-Efficient Future System Design. Springer.

[47]

D. Dasari, B. Akesson, V. Nélis, M. A. Awan, and S. M. Petters. 2013. Identifying the sources of unpredictability in COTS-based multicore systems. In Proceedings of the 8th IEEE International Symposium on Industrial Embedded Systems (SIES). 39--48.

[48]

D. Dasari and V. Nelis. 2012. An analysis of the impact of bus contention on the WCET in multicores. In Proceedings of the IEEE 14th International Conference on High Performance Computing and Communications (HPCC’12). 1450--1457.

[49]

M. Delvai, W. Huber, P. Puschner, and A. Steininger. 2003. Processor support for temporal predictability—The SPEAR design example. In Proceedings of the 15th Euromicro Conference on Real-Time Systems (ECRTS’03).

[50]

J. Diaz, C. Muñoz Caro, and A. Niño. 2012. A survey of parallel programming models and tools in the multi and many-core era. IEEE Trans. Parallel Distrib. Syst. 23, 8 (2012), 1369--1386.

Digital Library

[51]

EASA. 2011. Development Assurance of Airborne Electronic Hardware. EASA CM - SWCEH - 001, European Union Aviation Safety Agency (EASA). Retrieved from https://www.easa.europa.eu/sites/default/files/dfu/certification-docs-certification-memorandum-EASA-CM-SWCEH-001-Development-Assurance-of-Airborne-Electronic-Hardware.pdf.

[52]

EASA. 2013. Certification Memorandum—Software Aspects of Certification—EASA. Technical Report.

[53]

L. Ecco, S. Tobuschat, S. Saidi, and R. Ernst. 2014. A mixed critical memory controller using bank privatization and fixed priority scheduling. In Proceedings of the IEEE 20th International Conference on Embedded and Real-Time Computing Systems and Applications (RTCSA’14). 1--10.

[54]

M. El-Shambakey and B. Ravindran. 2012. STM concurrency control for embedded real-time software with tighter time bounds. In Proceedings of the 49th Design Automation Conference (DAC’12). ACM, 437--446.

[55]

EN 2011. EN50128—Railway Applications: Communication, signalling and processing systems—Software for railway control and protection systems.

[56]

Meinhard Erben, Wolf Günther, Tobias Sedlmeier, Dieter Lederer, and Klaus-Jürgen Amsler. 2006. Legal aspects of safety designed software development, especially under european law. In Proceedings of the 3rd European Embedded Real Time Software (ERTS’06). 6.

[57]

F. Eris, A. Joshi, A. B. Kahng, Y. Ma, S. Mojumder, and T. Zhang. 2018. Leveraging thermally-aware chiplet organization in 2.5D systems to reclaim dark silicon. In Proceedings of the Conference on Design, Automation and Test in Europe (DATE’18). 1441--1446.

[58]

H. Esmaeilzadeh, E. Blem, R. St. Amant, K. Sankaralingam, and D. Burger. 2012. Dark silicon and the end of multicore scaling. IEEE Micro 32, 3 (2012), 122--134.

Digital Library

[59]

M. Fakih, A. Lenz, M. Azkarate-Askasua, J. Coronel, A. Crespo, S. Davidmann, J. C. Diaz Garcia, N. Romero Gonzalez, K. Grüttner, S. Schreiner, R. Seyyedi, R. Obermaisser, A. Maleki, J. Öberg, M. T. Mohammadat, J. Perez-Cerrolaza, I. Sander, and I. Söderquist. 2017. SAFEPOWER project: Architecture for safe and power-efficient mixed-criticality systems. Microprocess. Microsyst. 52 (2017), 89--105.

Digital Library

[60]

G. Fernandez, J. Abella, E. Quiñones, C. Rochange, T. Vardanega, and F. J. Cazorla. 2014. Contention in multicore hardware shared resources: Understanding of the state of the art. In Proceedings of the 14th International Workshop on Worst-Case Execution Time Analysis, H. Falk (Ed.). 31--42.

[61]

Gabriel Fernandez, Javier Jalle, Jaume Abella, Eduardo Quiñones, Tullio Vardanega, and Francisco J. Cazorla. 2015. Increasing confidence on measurement-based contention bounds for real-time round-robin buses. In Proceedings of the 52nd Design Automation Conference (DAC’15). ACM.

[62]

S. Fisher. 2013. Certifying Applications in a Multi-Core Environment: A New Approach Gains Success. Technical Report. SYSGO AG.

[63]

G. Furano and A. Menicucci. 2018. Roadmap for On-Board Processing and Data Handling Systems in Space. Springer.

[64]

R. Ginosar. 2012. Survey of processors for space. In Proceedings of the Conference on Data Systems In Aerospace (DASIA’12).

[65]

S. Girbal, X. Jean, J. Le Rhun, D. Gracia Pérez, and M. Gatti. 2013. Deterministic platform software for hard real-time systems using multi-core COTS. In Proceedings of the IEEE/AIAA 32nd Digital Avionics Systems Conference (DASC’13). IEEE.

[66]

D. Gizopoulos, M. Psarakis, S. V. Adve, P. Ramachandran, S. K. S. Hari, D. Sorin, A. Meixner, A. Biswas, and X. Vera. 2011. Architectures for online error detection and recovery in multicore processors. In Proceedings of the Conference on Design, Automation and Test in Europe (DATE’11). 1--6.

[67]

K. Goossens, A. Azevedo, K. Chandrasekar, M. D. Gomony, S. Goossens, M. Koedam, Y. Li, D. Mirzoyan, A. Molnos, A. B. Nejad, A. Nelson, and S. Sinha. 2013. Virtual execution platforms for mixed-time-criticality systems: The CompSOC architecture and design flow. SIGBED Rev. 10, 3 (2013), 23--34.

Digital Library

[68]

K. Goossens, J. Dielissen, and A. Radulescu. 2005. Aethereal network on chip: Concepts, architectures, and implementations. IEEE Design Test Comput. 22, 5 (2005), 414--421.

Digital Library

[69]

K. Goossens and A. Hansson. 2010. The aethereal network on chip after ten years: Goals, evolution, lessons, and future. In Proceedings of the 47th Design Automation Conference (DAC’10). ACM, 306--311.

[70]

S. Goossens, B. Akesson, and K. Goossens. 2013. Conservative open-page policy for mixed time-criticality memory controllers. In Proceedings of the Conference on Design, Automation and Test in Europe (DATE’13). 525--530.

[71]

J. E. Gottschlich and D. A. Connors. 2008. Extending contention managers for user-defined priority-based transactions. In Proceedings of the Workshop on Exploiting Parallelism with Transactional Memory and other Hardware Assisted Methods (EPHAM’08).

[72]

Giovani Gracioli, Ahmed Alhammad, Renato Mancuso, Antônio Augusto Fröhlich, and Rodolfo Pellizzoni. 2015. A survey on cache management mechanisms for real-time embedded systems. ACM Comput. Surv. 48, 2 (2015).

[73]

E. Grade, A. Hayek, and J. Börcsök. 2016. Implementation of a fault-tolerant system using safety-related Xilinx tools conforming to the standard IEC 61508. In Proceedings of the International Conference on System Reliability and Science (ICSRS’16). 78--83.

[74]

P. Graydon and I. Bate. 2013. Safety assurance driven problem formulation for mixed-criticality scheduling. In Proceedings of the 1st International Workshop on Mixed Criticality Systems (WMC’13). 19--24.

[75]

Z. Gu and Q. Zhao. 2012. A state-of-the-art survey on real-time issues in embedded systems virtualization. J. Softw. Eng. Appl. 5, 1 (2012), 277--290.

[76]

S. Guertin and M. White. 2010. CMOS reliability challenges - The future of commercial digital electronics and NASA. In Proceedings of the NEPP Electronics Technology Workshop.

[77]

E. Hallet, G. Corradi, and S. McNeil. 2015. WP461—Xilinx Reduces Risk and Increases Efficiency for IEC61508 and ISO26262 Certified Safety Applications. Technical Report. Xilinx.

[78]

J. Han, M. Deubzer, J. Seo Park, J. Harnisch, and P. Leteinturier. 2014. Efficient multi-core software design space exploration for hybrid control unit integration. In SAE Tech. Paper.

[79]

A. Hayek and J. Börcsök. 2012. SRAM-based FPGA design techniques for safety related systems conforming to IEC 61508 a survey and analysis. In Proceedings of the 2nd International Conference on Advances in Computational Tools for Engineering Applications (ACTEA). 319--324.

[80]

A. Hayek and J. Börcsök. 2014. Safety chips in light of the standard IEC 61508: Survey and analysis. In Proceedings of the International Symposium on Fundamentals of Electrical Engineering (ISFEE’14). 1--6.

[81]

A. Hayek, B. Machmur, M. Schreiber, J. Börcsök, S. Gölz, and M. Epp. 2014. HICore1: Safety on a chip; turnkey solution for industrial control. In Proceedings of the IEEE 25th International Conference on Application-Specific Systems, Architectures, and Processors (ASAP’14). 74--75.

[82]

A. Hayek, M. Schreiber, B. Machmur, and J. Börcsök. 2013. Design and implementation of on-chip safety controller in terms of the standard IEC 61508. In Proceedings of the Conference on Recent Advances in Circuits; Systems and Automatic Control.

[83]

J. Henkel, L. Bauer, N. Dutt, P. Gupta, S. Nassif, M. Shafique, M. Tahoori, and N. Wehn. 2013. Reliable on-chip systems in the nano-era: Lessons learnt and future trends. In Proceedings of the 50th ACM/EDAC/IEEE Design Automation Conference (DAC’13). 1--10.

[84]

Carles Hernández, Jaume Abella, Francisco J. Cazorla, Alen Bardizbanyan, Jan Andersson, Fabrice Cros, and Franck Wartel. 2017. Design and implementation of a time predictable processor: Evaluation with a space case study. In Proceedings of the 29th Euromicro Conference on Real-Time Systems (ECRTS’17), Vol. 76. 16:1–16:23.

[85]

S. Hesham, J. Rettkowski, D. Goehringer, and M. A. Abd El Ghany. 2017. Survey on real-time networks-on-chip. IEEE Trans. Parallel Distrib. Syst. 28, 5 (2017), 1500--1517.

Digital Library

[86]

Salma Hesham, Jens Rettkowski, Diana Göhringer, and Mohamed A. Abd El Ghany. 2015. Survey on real-time network-on-chip architectures. In Applied Reconfigurable Computing, Kentaro Sano, Dimitrios Soudris, Michael Hübner, and Pedro C. Diniz (Eds.). Springer, Cham, 191--202.

[87]

C. Hilton and B. Nelson. 2006. PNoC: A flexible circuit-switched NoC for FPGA-based systems. IEEE Proc. Comput. Dig. Techn. 153, 3 (2006), 181--188.

[88]

P. Huyck. 2012. ARINC 653 and multi-core microprocessors—Considerations and potential impacts. In Proceedings of the IEEE/AIAA 31st Digital Avionics Systems Conference (DASC’12). 6B41–6B47.

[89]

IEC 2010. IEC 61508(-1/7): Functional safety of electrical/electronic/programmable electronic safety-related systems. Technical Report.

[90]

IEC 2018. IEC 62443-4-1: Security for industrial automation and control systems—Part 4-1: Secure product development lifecycle requirements. Technical Report.

[91]

Infineon. 2018. AURIX 32-bit Microcontrollers for Automotive and Industrial Applications. Technical Report. Infineon.

[92]

C. Iordanou, V. Soteriou, and K. Aisopos. 2014. Hermes: Architecting a top-performing fault-tolerant routing algorithm for networks-on-chips. In Proceedings of the IEEE 32nd International Conference on Computer Design (ICCD’14). 424--431.

[93]

ISO 2018. ISO 26262(-1/11) Road vehicles—Functional safety. Technical Report.

[94]

ITRS. 2018. International Roadmap for Devices and Systems—Executive Summary. Technical Report. IEEE.

[95]

X. Iturbe, B. Venu, J. Jagst, E. Ozer, P. Harrod, C. Turner, and J. Penton. 2018. Addressing functional safety challenges in autonomous vehicles with the Arm TCLS architecture. IEEE Design Test 35, 3 (2018), 7--14.

[96]

V. Izosimov, A. Paschalis, P. Reviriego, and H. Manhaeve. 2018. Application-Specific Solutions. Springer.

[97]

J. Jalle, E. Quinones, J. Abella, L. Fossati, M. Zulianello, and F. J. Cazorla. 2014. A dual-criticality memory controller (DCmc): Proposal and evaluation of a space case study. In Proceedings of the IEEE Real-Time Systems Symposium (RTSS’14). 207--217.

[98]

X. Jean. 2015. Hypervisor Control of COTS Multi-Cores Processors in Order to Enforce Determinism for Future Avionics Equipment. Ph.D. Dissertation. Telecom ParisTech.

[99]

X. Jean, M. Gatti, G. Berthon, and M. Fumey. 2011. The Use of Multicore Processors in Airborne Systems (EASA 2011.C31). Technical Report. EASA, Thales Avionics.

[100]

S. K. Jena and M. B. Srinivas. 2012. On the suitability of multi-core processing for embedded automotive systems. In Proceedings of the International Conference on Cyber-Enabled Distributed Computing and Knowledge Discovery (CyberC’12). 315--322.

[101]

R. Kalayappan and S. R. Sarangi. 2013. A survey of checker architectures. ACM Comput. Surv. 45, 4 (2013), 1--34.

Digital Library

[102]

B. Keller, M. Cochet, B. Zimmer, J. Kwak, A. Puggelli, Y. Lee, M. Blagojević, S. Bailey, P. F. Chiu, P. Dabbelt, C. Schmidt, E. Alon, K. Asanović, and B. Nikolić. 2017. A RISC-V processor SoC with integrated power management at submicrosecond timescales in 28 nm FD-SOI. IEEE J. Solid-State Circ. 52, 7 (2017), 1863--1875.

[103]

S. Kiamehr, M. B. Tahoori, and L. Anghel. 2018. Manufacturing Threats. Springer.

[104]

L. M. Kinnan. 2009. Use of multicore processors in avionics and its potential impact on implementation and certification. SAE Tech. Papers (2009).

[105]

Hermann Kopetz. 2019. Simplicity is Complex: Foundations of Cyber-Physical System Design. Springer.

[106]

Leonidas Kosmidis, Jerome Lachaize, Jaume Abella, Olivier Notebaert, Francisco J. Cazorla, and David Steenari. 2019. GPU4S: Embedded GPUs in space. In Proceedings of the 22nd Euromicro Conference on Digital Systems Design (DSD’19).

[107]

O. Kotaba, J. Nowotsch, M. Paulitsch, S. M. Petters, and H. Theilingx. 2013. Multicore in real-time systems - Temporal isolation challenges due to shared resources. In Proceedings of the Workshop on Industry-Driven Approaches for Cost-effective Certification of Safety-Critical, Mixed-Criticality Systems (WICERT’13).

[108]

S. Kriaa, L. Pietre-Cambacedes, M. Bouissou, and Y. Halgand. 2015. A survey of approaches combining safety and security for industrial control systems. Rel. Eng. Syst. Safety 139 (2015), 156--178.

[109]

K. Lakshmanan, S. Kato, and R. Rajkumar. 2010. Scheduling parallel real-time tasks on multi-core processors. In Proceedings of the 31st IEEE Real-Time Systems Symposium 259--268.

[110]

A. Larrucea, I. Agirre, C. F. Nicolas, J. Perez, M. Azkarate-Askasua, and T. Trapman. 2015. Temporal independence validation of an IEC-61508 compliant mixed-criticality system based on multicore partitioning. In Proceedings of the Forum on Specification and Design Languages (FDL’15). 1--8.

[111]

A. Larrucea, I. Martinez, H. Ahmadian, R. Obermaisser, V. Brocal, S. Peiró, and J. Perez. 2016. DREAMS: Cross-domain mixed-criticality patterns. In Proceedings of the Mixed-Criticality Workshop on Real Time System Symposium (RTSS’16).

[112]

A. Larrucea, I. Martinez, R. Obermaisser, J. Perez, and C. F. Nicolas. 2017. Modular development of dependable mixed-criticality embedded systems. In Proceedings of the 20th Euromicro Conference on Digital Systems Design (DSD’17). 419--426.

[113]

A. Larrucea, J. Perez, I. Agirre, V. Brocal, and R. Obermaisser. 2015. A modular safety case for an IEC 61508 compliant generic hypervisor. In Proceedings of the 18th Euromicro Conference on Digital Systems Design (DSD’15). 571--574.

[114]

A. Larrucea, J. Perez, and R. Obermaisser. 2015. A modular safety case for an IEC 61508 compliant COTS multi-core device. In Proceedings of the 13th International Conference on Dependable, Autonomatic and Secure Computing (DASC’15). 8.

[115]

A. Larrucea, J. Perez, and R. Obermaisser. 2015. A modular safety case for an IEC 61508 compliant generic COTS processor. In Proceedings of the IEEE International Conference on Computing and Information Technology; Ubiquitous Computing and Communication; Dependable, Autonomic and Secure Computing; Pervasive Intellegence and Computing (CIT/IUCC/DASC/PICom’15). 1788--1795.

[116]

E. A. Lee. 2008. Cyber physical systems: Design challenges. In Proceedings of the 11th IEEE International Symposium on Object Oriented Real-Time Distributed Computing (ISORC’08). 363--369.

Digital Library

[117]

Ikhwan Lee, Michael Sullivan, Evgeni Krimer, Dong Wan Kim, Mehmet Basoglu, Doe Hyun Yoon, Larry Kaplan, and Mattan Erez. 2012. Survey of Error and Fault Detection Mechanisms. Technical Report. The University of Texas. Retrieved from http://lph.ece.utexas.edu/merez/uploads/MattanErez/detection_mechanisms_TR_LPH_2011_002.pdf.

[118]

P. Leteinturier, S. Brewerton, and K. Scheibert. 2008. MultiCore benefits 8 challenges for automotive applications. In SAE Tech. Paper.

[119]

Paul S. Levy. 2017. WP495—Using Zynq-7000 SoC IEC 61508 Artifacts to Achieve ISO 13849 Compliance. Technical Report. Xilinx.

[120]

Y. Li, B. Akesson, and K. Goossens. 2014. Dynamic command scheduling for real-time memory controllers. In Proceedings of the 26th Euromicro Conference on Real-Time Systems (ECRTS’14). 3--14.

[121]

I. Liu, J. Reineke, D. Broman, M. Zimmer, and E. A. Lee. 2012. A PRET microarchitecture implementation with repeatable timing and competitive performance. In Proceedings of the IEEE 30th International Conference on Computer Design (ICCD’12). 87--93.

[122]

I. Liu, J. Reineke, and E. A. Lee. 2010. A PRET architecture supporting concurrent programs with composable timing properties. In Proceedings of the 44th Asilomar Conference on Signals, Systems, and Computing (ASILOMAR’10). 2111--2115.

[123]

A. Löfwenmark and S. Nadjm-Tehrani. 2018. Fault and timing analysis in critical multi-core systems: A survey with an avionics perspective. J. Syst. Architect. 87 (2018), 1--11.

[124]

H. Lu. 2013. Low-Cost Highly-Efficient Fault Tolerant Processor Design for Mitigating the Reliability Issues in Nanometric Technologies. Thesis, Université de Grenoble.

[125]

G. Macher, M. Bachinger, and M. Stolz. 2017. Embedded multi-core system for design of next-generation powertrain control units. In Proceedings of the 13th European Dependable Computing Conference (EDCC’17). 66--72.

[126]

G. Macher, A. Höller, E. Armengaud, and C. Kreiner. 2015. Automotive embedded software: Migration challenges to multi-core computing platforms. In Proceedings of the IEEE 13th International Conference on Industrial Informatics (INDIN’15). 1386--1393.

[127]

A. Maheshwari, W. Burleson, and R. Tessier. 2004. Trading off transient fault tolerance and power consumption in deep submicron (DSM) VLSI circuits. IEEE Trans. Very Large Scale Integr. Syst. 12, 3 (2004), 299--311.

Digital Library

[128]

Claire Maiza, Hamza Rihani, Juan M. Rivas, Joël Goossens, Sebastian Altmeyer, and Robert I. Davis. 2019. A survey of timing verification techniques for multi-core real-time systems. ACM Comput. Surv. 52, 3 (2019).

[129]

R. Mariani, G. Boschi, and F. Colucci. 2007. Using an innovative SoC-level FMEA methodology to design in compliance with IEC 61508. In Proceedings of the Conference on Design, Automation and Test in Europe (DATE’07). 1--6.

[130]

Arya Mazaheri, Johannes Schulte, Matthew Moskewicz, Felix Wolf, and Ali Jannesari. 2019. Enhancing the programmability and performance portability of GPU tensor operations. In Proceedings of the 25th Euro-Par Conference (Lecture Notes in Computer Science), Vol. 11725. Springer, 213--226.

[131]

A. Meixner, M. E. Bauer, and D. Sorin. 2007. Argus: Low-cost, comprehensive error detection in simple cores. In Proceedings of the 40th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO’07). 210--222.

Digital Library

[132]

S. Metzlaff, S. Weis, and T. Ungerer. 2013. Leveraging transactional memory for a predictable execution of applications composed of hard real-time and best-effort tasks. In Proceedings of the 21st International Conference on Real-Time Networks and Systems (RTNS’13). ACM, 45--54.

[133]

M. Millberg, E. Nilsson, R. Thid, and A. Jantsch. 2004. Guaranteed bandwidth using looped containers in temporally disjoint networks within the nostrum network on chip. In Proceeding of the Conference on Design, Automation and Test in Europe (DATE’04), Vol. 2. 890--895.

[134]

T. Mitra, J. Teich, and L. Thiele. 2018. Time-critical systems design: A survey. IEEE Design Test 35, 2 (2018), 8--26.

[135]

S. Mittal. 2016. A survey of recent prefetching techniques for processor caches. ACM Comput. Surv. 49, 2 (2016).

[136]

S. Mittal. 2017. A survey of techniques for cache partitioning in multicore processors. ACM Comput. Surv. 50, 2 (2017).

[137]

Sparsh Mittal and Jeffrey S. Vetter. 2015. A survey of CPU-GPU heterogeneous computing techniques. ACM Comput. Surv. 47, 4 (2015).

[138]

S. R. Msirdi. 2017. Modular Avionics Software Integration on Multi-Core COTS: Certification-Compliant Methodology and Timing Analysis Metrics for Legacy Software Reuse in Modern Aerospace Systems. Thesis, Université de Toulouse.

[139]

Imanol Mugarza, Jorge Parra, and Eduardo Jacob. 2017. Software updates in safety and security co-engineering. In Computer Safety, Reliability, and Security, Stefano Tonetta, Erwin Schoitsch, and Friedemann Bitsch (Eds.). Springer, Cham, 199--210.

[140]

H. Mushtaq, Z. Al-Ars, and K. Bertels. 2015. Calculation of worst-case execution time for multicore processors using deterministic execution. In Proceedings of the 25th International Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS’15). 33--39.

[141]

G. Nelissen, D. Pereira, and L. M. Pinho. 2015. A novel run-time monitoring architecture for safe and efficient inline monitoring. In Reliable Software Technologies—Ada-Europe, Juan Antonio de la Puente and Tullio Vardanega (Eds.). Springer, 66--82.

[142]

T. S. Nidhin, Anindya Bhattacharyya, R. P. Behera, and T. Jayanthi. 2018. A review on SEU mitigation techniques for FPGA configuration memory. IETE Tech. Rev. 35, 2 (2018), 157--168.

[143]

J. Nowotsch and M. Paulitsch. 2012. Leveraging multi-core computing architectures in avionics. In Proceedings of the 9th European Dependable Computing Conference (EDCC’12). 132--143.

[144]

R. Obermaisser, C. El Salloum, B. Huber, and H. Kopetz. 2008. The time-triggered system-on-a-chip architecture. In Proceedings of the IEEE International Symposium on Industrial Electronics (ISIE’08). 1941--1947.

[145]

R. Obermaisser, C. El Salloum, B. Huber, and H. Kopetz. 2009. From a federated to an integrated automotive architecture. IEEE Trans. Comput.-Aided Design Integr. Circ. Syst. 28, 7 (2009), 956--965.

Digital Library

[146]

M. Ottavi, D. Gizopoulos, and S. Pontarelli. 2018. Dependable Multicore Architectures at Nanoscale. Springer.

[147]

M. Ottavi, S. Pontarelli, D. Gizopoulos, C. Bolchini, M. K. Michael, L. Anghel, M. Tahoori, A. Paschalis, P. Reviriego, O. Bringmann, V. Izosimov, H. Manhaeve, C. Strydis, and S. Hamdioui. 2015. Dependable multicore architectures at nanoscale: The view from europe. IEEE Design Test 32, 2 (2015), 17--28.

[148]

Z. Owda and R. Obermaisser. 2017. Mixed-criticality transactional memory controller for embedded systems. In IEEE International Conference on Industrial Informatics (INDIN'17). 104--110.

[149]

I. Oz and S. Arslan. 2019. A survey on multithreading alternatives for soft error fault tolerance. ACM Comput. Surv. 52, 2 (2019), 1--38.

Digital Library

[150]

Haluk Ozaktas, Christine Rochange, and Pascal Sainrat. 2013. Automatic WCET analysis of real-time parallel applications. In Proceedings of the 13th International Workshop on Worst-Case Execution Time Analysis (WCET’13).

[151]

Miloš Panić, Sebastian Kehr, Eduardo Quiñones, Bert Boddecker, Jaume Abella, and Francisco J. Cazorla. 2014. RunPar: An allocation algorithm for automotive applications exploiting runnable parallelism in multicores. In Proceedings of the International Conference on Hardware/Software Codesign and System Synthesis (CODES’14). ACM, Article 29, 10 pages.

[152]

M. Paolieri, J. Mische, S. Metzlaff, M. Gerdes, E. Quiñones, S. Uhrig, T. Ungerer, and F. J. Cazorla. 2013. A hard real-time capable multi-core SMT processor. ACM Trans. Embed. Comput. Syst. 12, 3 (2013).

Digital Library

[153]

M. Paolieri, E. Quinones, F. J. Cazorla, and M. Valero. 2009. An analyzable memory controller for hard real-time CMPs. IEEE Embed. Syst. Lett. 1, 4 (2009), 86--90.

Digital Library

[154]

C. Paukovits. 2008. The Time-triggered System-on-chip Architecture. Thesis. Institut für Technische Informatik.

[155]

M. Paulitsch, O. M. Duarte, H. Karray, K. Mueller, D. Muench, and J. Nowotsch. 2015. Mixed-criticality embedded systems—A balance ensuring partitioning and performance. In Proceedings of the Euromicro Conference on Digital System Design (DSD’15). 453--461.

[156]

R. Pellizzoni, A. Schranzhofer, Chen Jian-Jia, M. Caccamo, and L. Thiele. 2010. Worst case delay analysis for memory interference in multicore systems. In Proceedings of the Conference on Design, Automation and Test in Europe (DATE’10). 741--746.

[157]

J. Perez, M. Coppola, M. Faugère, D. Gracia Perez, M. Grammatikakis, A. Larrucea Ortube, A. Mouzakitis, A. Papagrigoriou, P. Petrakis, V. Piperaki, I. Sarasola, and G. Tsamis. 2018. Evaluation. CRC Press.

[158]

J. Perez, D. Gonzalez, C. F. Nicolas, T. Trapman, and J. M. Garate. 2014. A safety certification strategy for IEC-61508 compliant industrial mixed-criticality systems based on multicore partitioning. In Proceedings of the 17th Euromicro Conference on Digital Syst. Design (DSD’14). 394--400.

[159]

J. Perez, D. Gonzalez, S. Trujillo, and A. Trapman. 2015. A Safety Concept for an IEC 61508 Compliant Fail-safe Wind Power Mixed-criticality Embedded System Based on Multi-core Partitioning. Lecture Notes in Computer Science, Vol. 9111. Springer. 3–17.

[160]

S. Pinto, A. Oliveira, J. Pereira, J. Cabral, J. Monteiro, and A. Tavares. 2017. Lightweight multicore virtualization architecture exploiting ARM TrustZone. In Proceedings of the 43rd IEEE Industrial Electronics Society (IECON’17). 3562--3567.

[161]

A. Platschek, N. Mc Guire, and L. Bulwahn. 2018. Certifying Linux: Lessons learned in three years of SIL2LinuxMP. In Proceedings of the Embedded World Conference.

[162]

S. Pontarelli, Juan A. Maestro, and P. Reviriego. 2018. Dependability Solutions. Springer.

[163]

B. Krishna Priya, Amit D. Joshi, and N. Ramasubramanian. 2016. A survey on performance of on-chip cache for multi-core architectures. In Proceedings of the International Conference on Informatics and Analytics (ICIA’16). ACM.

[164]

Roger Pujol, Hamid Tabani, Leonidas Kosmidis, Enrico Mezzetti, Jaume Abella, and Francisco J. Cazorla. 2019. Generating and exploiting deep learning variants to increase heterogeneous resource utilization in the NVIDIA Xavier. In Proceedings of the 31st Euromicro Conference on Real-Time Systems (ECRTS’19) (Leibniz International Proceedings in Informatics (LIPIcs)), Sophie Quinton (Ed.), Vol. 133. Schloss Dagstuhl–Leibniz-Zentrum fuer Informatik, Dagstuhl, Germany, 23:1–23:23.

[165]

P. Puschner. 2013. Embedded systems for safety-critical and mixed-criticality applications. In Proceedings of the 2nd Mediterranean Conference on Embedded Computers (MECO’13). 1--2.

[166]

P. Puschner, B. Cilku, and D. Prokesch. 2016. Constructing time-predictable MPSoCs: Avoid conflicts in temporal control. In Proceedings of the IEEE 10th International Symposium on Embedded Multicore/Many-core Systems-on-Chip (MCSOC’16). 321--328.

[167]

Arthur Pyka, Mathias Rohde, and Sascha Uhrig. 2014. A real-time capable coherent data cache for multicores. Concurr. Comput.: Pract. Exper. 26, 6 (2014), 1342--1354.

Digital Library

[168]

Eduardo Quiñones, Marko Bertogna, Erez Hadad, Ana Juan Ferrer, Luca Chiantore, and Alfredo Reboa. 2018. Big data analytics for smart cities: The H2020 CLASS project. In Proceedings of the 11th ACM International Systems and Storage Conference (SYSTOR’18). ACM, 130.

Digital Library

[169]

S. Royuela, A. Duran, M. A. Serrano, E. Quiñones, and X. Martorell. 2017. A Functional Safety OpenMP* for Critical Real-Time Embedded Systems. Springer, Book section 16.

[170]

S. Saidi, R. Ernst, S. Uhrig, H. Theiling, and B. D. de Dinechin. 2015. The shift to multicores in real-time and safety-critical systems. In Proceedings of the 10th International Conference on Hardware/Software Codesign and System Synthesis. IEEE Press, 220--229.

[171]

O. Sander, F. Bapp, L. Dieudonne, T. Sandmann, and J. Becker. 2017. The promised future of multi-core processors in avionics systems. CEAS Aeronaut. J. 8, 1 (2017), 143--155.

[172]

I. Schagaev and T. Kaegi-Trachsel. 2016. Software Design for Resilient Computer Systems. Springer.

[173]

K. Schmidt, J. Harnisch, D. Marx, A. Mayer, A. Kohn, and R. Deml. 2014. Timing analysis and tracing concepts for ECU development. SAE World Congr. Exhibit. 1 (2014).

[174]

M. Schoeberl, S. Abbaspour, B. Akesson, N. Audsley, R. Capasso, J. Garside, K. Goossens, S. Goossens, S. Hansen, R. Heckmann, S. Hepp, B. Huber, A. Jordan, E. Kasapaki, J. Knoop, Y. Li, D. Prokesch, W. Puffitsch, P. Puschner, A. Rocha, C. Silva, J. Sparsø, and A. Tocchi. 2015. T-CREST: Time-predictable multi-core architecture for embedded systems. J. Syst. Architect. 61, 9 (2015), 449--471.

Digital Library

[175]

M. Schoeberl, W. Puffitsch, S. Hepp, B. Huber, and D. Prokesch. 2018. Patmos: A time-predictable microprocessor. Real-Time Syst. 54, 2 (2018), 389--423.

Digital Library

[176]

Erwin Schoitsch. 2013. D6.1—State of the Art for System Qualification and Certification, V8V Survey (EMC2). Technical Report.

[177]

A. Scolari, F. Sironi, D. Sciuto, and M. D. Santambrogio. 2014. A survey on recent hardware and software-level cache management techniques. In Proceedings of the IEEE International Symposium on Parallel and Distributed Processing with Applications.242--247.

[178]

Maria A. Serrano, Sara Royuela, and Eduardo Quinones. 2018. Towards an OpenMP specification for critical real-time systems. In Proceedings of the 14th International Workshop on OpenMP (IWOMP’18). 143--159.

[179]

Z. Shi and A. Burns. 2008. Real-time communication analysis for on-chip networks with wormhole switching. In Proceedings of the 2nd ACM/IEEE International Symposium on Networks-on-Chip (NOCS’08). 161--170.

[180]

M. Slijepcevic, L. Kosmidis, J. Abella, E. Quinones, and F. J. Cazorla. 2014. Timing verification of fault-tolerant chips for safety-critical applications in harsh environments. IEEE Micro 34, 6 (2014), 8--19.

[181]

Daniel J. Sorin. 2009. Fault Tolerant Computer Architecture. Morgan 8 Claypool Publishers.

[182]

V. Sridharan and S. Gurumurthi. 2018. Resilience Proportionality—A Paradigm for Efficient and Reliable System Design. Springer.

[183]

H. Sutter and J. Larus. 2005. Software and the concurrency revolution. Queue 3, 7 (2005), 54--62.

Digital Library

[184]

S. Trujillo, A. Crespo, A. Alonso, and J. Perez. 2014. MultiPARTES: Multi-core partitioning and virtualization for easing the certification of mixed-criticality systems. Microprocess. Microsyst. 38, 8, Part B (2014), 921--932.

[185]

G. Tsamis, S. Kavvadias, A. Papagrigoriou, M. D. Grammatikakis, and K. Papadimitriou. 2016. Efficient bandwidth regulation at memory controller for mixed criticality applications. In Proceedings of the 11th International Symposium on Reconfigurable Communication-centric Systems-on-Chip (ReCoSoC’16). 1--8.

[186]

Theo Ungerer, Christian Bradatsch, Martin Frieb, Florian Kluge, Jörg Mische, Alexander Stegmeier, Ralf Jahr, Mike Gerdes, Pavel Zaykov, Lucie Matusova, Zai Jian Jia Li, Zlatko Petrov, Bert Böddeker, Sebastian Kehr, Hans Regler, Andreas Hugl, Christine Rochange, Haluk Ozaktas, Hugues Cassé, Armelle Bonenfant, Pascal Sainrat, Nick Lay, David George, Ian Broster, Eduardo Quiñones, Milos Panic, Jaume Abella, Carles Hernandez, Francisco Cazorla, Sascha Uhrig, Mathias Rohde, and Arthur Pyka. 2016. Parallelizing industrial hard real-time applications for the parMERASA multicore. ACM Trans. Embed. Comput. Syst. 15, 3 (2016).

Digital Library

[187]

A. Vajda. 2011. Multi-core and Many-core Processor Architectures. Springer US, Boston, MA, 9--43.

[188]

P. K. Valsan, H. Yun, and F. Farshchi. 2016. Taming non-blocking caches to improve isolation in multicore real-time systems. In Proceedings of the IEEE Real-Time and Embedded Technology and Applications Symposium (RTAS’16). 1--12.

[189]

F. Wartel, L. Kosmidis, A. Gogonel, A. Baldovino, Z. Stephenson, B. Triquet, E. Quinones, C. Lo, E. Mezzetta, I. Broster, J. Abella, L. Cucu-Grosjean, T. Vardanega, and F. J. Cazorla. 2015. Timing analysis of an avionics case study on complex hardware/software platforms. In Proceedings of the Conference on Design, Automation and Test in Europe (DATE’15). 397--402.

[190]

F. Wartel, L. Kosmidis, C. Lo, B. Triquet, E. Quinones, J. Abella, A. Gogonel, A. Baldovin, E. Mezzetti, L. Cucu, T. Vardanega, and F. J. Cazorla. 2013. Measurement-based probabilistic timing analysis: Lessons from an integrated-modular avionics case study. In Proceedings of the 8th IEEE International Symposium on Industrial Embedded Systems (SIES’13). 241--248.

[191]

Saud Wasly. 2018. Architecture Design for Distributed Mixed-criticality Systems Based on Multi-core Chips. Thesis, Universität Siegen.

[192]

Raphael Weber. 2019. ARAMIS II. Tool interoperability and exchange formats. In Proceedings of the International Workshop on Automated Engineering of Autonomic and Run-time Evolving Systems. Final Workshop, Stuttgart.

[193]

W. Weber, A. Hoess, J. v. Deventer, F. Oppenheimer, R. Ernst, A. Kostrzewa, P. Dore, T. Goubier, H. Isakovic, N. Druml, E. Wuchner, D. Schneider, E. Schoitsch, E. Armengaud, T. Soderqvist, M. Traversone, S. Uhrig, J. C. Perez-Cortes, S. Saez, J. Kuusela, M. v. Helvoort, X. Cai, B. Nordmoen, G. Y. Paulsen, H. P. Dahle, M. Geissel, J. Salecker, and P. Tummeltshammer. 2016. The EMC2 project on embedded microcontrollers: Technical progress after two years. In Proceedings of the Euromicro Conference on Digital Systems Design (DSD’16). 524--531.

[194]

D. Wentzlaff, P. Griffin, H. Hoffmann, L. Bao, B. Edwards, C. Ramey, M. Mattina, C. C. Miao, J. F. Brown III, and A. Agarwal. 2007. On-chip interconnection architecture of the tile processor. IEEE Micro 27, 5 (2007), 15--31.

[195]

R. Wilhelm, J. Engblom, A. Ermedahl, N. Holsti, S. Thesing, D. Whalley, G. Bernat, C. Ferdinand, R. Heckmann, T. Mitra, F. Mueller, I. Puaut, P. Puschner, J. Staschulat, and P. Stenstr. 2008. The worst-case execution-time problem—Overview of methods and survey of tools. ACM Trans. Embed. Comput. Syst. 7, 3 (2008), 1--53.

Digital Library

[196]

J. Windsor, K. Eckstein, P. Mendham, and T. Pareaud. 2011. Time and space partitioning security components for spacecraft flight software. In Proceedings of the 30th IEEE/AIAA Digital Avionics Systems Conference (DASC’11). 8A5–1–8A5–14.

[197]

W. Wolf, A. A. Jerraya, and G. Martin. 2008. Multiprocessor system-on-chip (MPSoC) technology. IEEE Trans. Comput.-Aided Design Integr. Circ. Syst. 27, 10 (2008), 1701--1713.

Digital Library

[198]

Xilinx. 2018. UG1085—Zynq UltraScale+ Device—Technical Reference Manual. Technical Report. Xilinx.

[199]

Xilinx. 2018. UG116—Device Reliability Report—First Half 2018. Technical Report. Xilinx.

[200]

H. Yun. 2013. Improving Real-Time Performance on Multicore Platforms Using MemGuard. Retrieved from http://www.ittc.ku.edu/%7Eheechul/papers/memguard-rtlws13.pdf.

[201]

H. Yun, G. Yao, R. Pellizzoni, M. Caccamo, and L. Sha. 2013. MemGuard: Memory bandwidth reservation system for efficient performance isolation in multi-core platforms. In Proceedings of the IEEE 19th Real-Time and Embedded Technology and Applications Symposium (RTAS’13). 55--64.

[202]

H. Yun, G. Yao, R. Pellizzoni, M. Caccamo, and L. Sha. 2016. Memory bandwidth management for efficient performance isolation in multi-core platforms. In IEEE Trans. Comput. IEEE, 562--576.

Digital Library

[203]

R. Zalman, A. Griessing, and P. Emberson. 2011. Timing correctness in safety-related automotive software. In SAE Tech. Papers. SAE.

[204]

M. Zimmer, D. Broman, C. Shaver, and E. A. Lee. 2014. FlexPRET: A processor platform for mixed-criticality systems. In Proceedings of the IEEE 19th Real-Time and Embedded Technology and Applications Symposium (RTAS’14). 101--110.

[205]

M. P. Zimmer. 2015. Predictable Processors for Mixed-Criticality Systems and Precision-Timed I/O. Thesis, University of California, Berkeley.

Cited By

Liu YLi XFang J(2024)Deep-Autoencoder-Based Radar Source Recognition: Addressing Large-Scale Imbalanced Data and Edge Computing ConstraintsElectronics10.3390/electronics1315289113:15(2891)Online publication date: 23-Jul-2024
https://doi.org/10.3390/electronics13152891
Wu ZKaushik APatel H(2024)High Performance and Predictable Shared Last-level Cache for Safety-Critical SystemsACM Transactions on Embedded Computing Systems10.1145/368730823:6(1-30)Online publication date: 11-Sep-2024
https://dl.acm.org/doi/10.1145/3687308
Perez-Cerrolaza JAbella JBorg MDonzella CCerquides JCazorla FEnglund CTauber MNikolakopoulos GFlores J(2024)Artificial Intelligence for Safety-Critical Systems in Industrial and Transportation Domains: A SurveyACM Computing Surveys10.1145/362631456:7(1-40)Online publication date: 9-Apr-2024
https://dl.acm.org/doi/10.1145/3626314
Show More Cited By

Index Terms

Multi-core Devices for Safety-critical Systems: A Survey
1. Computer systems organization
2. Hardware
  1. Robustness
    1. Safety critical systems

Recommendations

GPU Devices for Safety-Critical Systems: A Survey
Graphics Processing Unit (GPU) devices and their associated software programming languages and frameworks can deliver the computing performance required to facilitate the development of next-generation high-performance safety-critical systems such as ...
Collision Analysis of Safety Devices to Prevent Hazards in Safety Critical Systems
SERE '14: Proceedings of the 2014 Eighth International Conference on Software Security and Reliability

The importance of safety-critical systems is increasing, as seen with the terrible accidents recently occurring in nuclear power plants and with airplanes. To ensure the safety of those systems, system engineers should consider how to prevent system ...
Integrated safety analysis of software-controlled critical systems

Software for safety-critical systems must deal with the hazards identified by safety analysis in order to make the system safe, risk-free and fail-safe. Certain faults in critical systems can result in catastrophic consequences such as death, injury or ...

Comments

Please enable JavaScript to view thecomments powered by Disqus.

Information & Contributors

Information

Published In

cover image ACM Computing Surveys

ACM Computing Surveys Volume 53, Issue 4

July 2021

831 pages

ISSN:0360-0300

EISSN:1557-7341

DOI:10.1145/3410467

Editor:
Albert Zomaya
University of Sydney, Australia

Issue’s Table of Contents

Copyright © 2020 ACM.

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

Publisher

Association for Computing Machinery

New York, NY, United States

Publication History

Published: 03 August 2020

Online AM: 13 May 2020

Accepted: 01 May 2020

Revised: 01 March 2020

Received: 01 October 2019

Published in CSUR Volume 53, Issue 4

Permissions

Request permissions for this article.

Request Permissions

Check for updates

Author Tags

Qualifiers

Survey
Research
Refereed

Funding Sources

Ekonomiaren Garapen eta Lehiakortasun Saila, Eusko Jaurlaritza
Spanish Ministry of Economy and Competitiveness
HiPEAC Network of Excellence

Contributors

Other Metrics

View Article Metrics

Bibliometrics & Citations

Bibliometrics

Article Metrics

37
Total Citations
View Citations
1,087
Total Downloads

Downloads (Last 12 months)221
Downloads (Last 6 weeks)13

Reflects downloads up to 24 Sep 2024

Other Metrics

View Author Metrics

Citations

Cited By

Liu YLi XFang J(2024)Deep-Autoencoder-Based Radar Source Recognition: Addressing Large-Scale Imbalanced Data and Edge Computing ConstraintsElectronics10.3390/electronics1315289113:15(2891)Online publication date: 23-Jul-2024
https://doi.org/10.3390/electronics13152891
Wu ZKaushik APatel H(2024)High Performance and Predictable Shared Last-level Cache for Safety-Critical SystemsACM Transactions on Embedded Computing Systems10.1145/368730823:6(1-30)Online publication date: 11-Sep-2024
https://dl.acm.org/doi/10.1145/3687308
Perez-Cerrolaza JAbella JBorg MDonzella CCerquides JCazorla FEnglund CTauber MNikolakopoulos GFlores J(2024)Artificial Intelligence for Safety-Critical Systems in Industrial and Transportation Domains: A SurveyACM Computing Surveys10.1145/362631456:7(1-40)Online publication date: 9-Apr-2024
https://dl.acm.org/doi/10.1145/3626314
Leon GBadia JBelloch JGarcia-Valderas MLindoso AEntrena L(2024)Analyzing the Influence of Memory and Workload on the Reliability of GPUs Under Neutron RadiationIEEE Transactions on Nuclear Science10.1109/TNS.2024.338749071:8(1487-1495)Online publication date: Aug-2024
https://doi.org/10.1109/TNS.2024.3387490
Yu YLakemond NHolmberg G(2024)AI in the Context of Complex Intelligent Systems: Engineering Management ConsequencesIEEE Transactions on Engineering Management10.1109/TEM.2023.3268340(1-14)Online publication date: 2024
https://doi.org/10.1109/TEM.2023.3268340
Wang XWu ZPellizzoni RPatel H(2024)Exclusive Hierarchies for Predictable Sharing in Last-Level Cache2024 IEEE 30th Real-Time and Embedded Technology and Applications Symposium (RTAS)10.1109/RTAS61025.2024.00023(186-198)Online publication date: 13-May-2024
https://doi.org/10.1109/RTAS61025.2024.00023
Sinha SDwivedi SAzizian M(2024)Towards Deterministic End-to-end Latency for Medical AI Systems in NVIDIA Holoscan2024 ACM/IEEE 15th International Conference on Cyber-Physical Systems (ICCPS)10.1109/ICCPS61052.2024.00028(235-246)Online publication date: 13-May-2024
https://doi.org/10.1109/ICCPS61052.2024.00028
Marques FRodríguez MSá BPinto S(2024)“Interrupting” the Status Quo: A First Glance at the RISC-V Advanced Interrupt Architecture (AIA)IEEE Access10.1109/ACCESS.2024.335211412(9822-9833)Online publication date: 2024
https://doi.org/10.1109/ACCESS.2024.3352114
Abella JPerez JEnglund CZonooz BGiordana GDonzella CCazorla FMezzetti ESerra IBrando AAgirre IEizaguirre FBui TArani ESarfraz FBalasubramaniam ABadar ABloise IFeruglio LCinelli IBrighenti DCunial D(2023)SAFEXPLAIN: Safe and Explainable Critical Embedded Systems Based on AI2023 Design, Automation & Test in Europe Conference & Exhibition (DATE)10.23919/DATE56975.2023.10137128(1-6)Online publication date: Apr-2023
https://doi.org/10.23919/DATE56975.2023.10137128
Wu ZBekmyrza MKapre NPatel H(2023)Ditty: Directory-based Cache Coherence for Multicore Safety-critical Systems2023 Design, Automation & Test in Europe Conference & Exhibition (DATE)10.23919/DATE56975.2023.10136986(1-6)Online publication date: Apr-2023
https://doi.org/10.23919/DATE56975.2023.10136986
Show More Cited By

View Options

Get Access

Login options

Check if you have access through your login credentials or your institution to get full access on this article.

Full Access

Get this Article

View options

PDF

View or Download as a PDF file.

eReader

View online with eReader.

HTML Format

View this article in HTML Format.

Media

Figures

Other

Tables

View Issue’s Table of Contents