research-article

NeuPow: A CAD Methodology for High-level Power Estimation Based on Machine Learning

Authors:

Jean-Christophe Prévotet,

Francesca Palumbo,

Maryline Hélard,

Luigi RaffoAuthors Info & Claims

ACM Transactions on Design Automation of Electronic Systems (TODAES), Volume 25, Issue 5

Article No.: 41, Pages 1 - 29

https://doi.org/10.1145/3388141

Published: 03 August 2020 Publication History

Abstract

In this article, we present a new, simple, accurate, and fast power estimation technique that can be used to explore the power consumption of digital system designs at an early design stage. We exploit the machine learning techniques to aid the designers in exploring the design space of possible architectural solutions, and more specifically, their dynamic power consumption, which is application-, technology-, frequency-, and data-stimuli dependent. To model the power and the behavior of digital components, we adopt the Artificial Neural Networks (ANNs), while the final target technology is Application Specific Integrated Circuit (ASIC). The main characteristic of the proposed method, called NeuPow, is that it relies on propagating the signals throughout connected ANN models to predict the power consumption of a composite system. Besides a baseline version of the NeuPow methodology that works for a given predefined operating frequency, we also derive an upgraded version that is frequency-aware, where the same operating frequency is taken as additional input by the ANN models. To prove the effectiveness of the proposed methodology, we perform different assessments at different levels. Moreover, technology and scalability studies have been conducted, proving the NeuPow robustness in terms of these design parameters. Results show a very good estimation accuracy with less than 9% of relative error independently from the technology and the size/layers of the design. NeuPow is also delivering a speed-up factor of about 84× with respect to the classical power estimation flow.

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Index Terms

NeuPow: A CAD Methodology for High-level Power Estimation Based on Machine Learning
1. Hardware
  1. Power and energy
    1. Power estimation and optimization
      1. Circuits power issues

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Information & Contributors

Information

Published In

cover image ACM Transactions on Design Automation of Electronic Systems

ACM Transactions on Design Automation of Electronic Systems Volume 25, Issue 5

Special Issue on Machine Learning

September 2020

303 pages

ISSN:1084-4309

EISSN:1557-7309

DOI:10.1145/3409648

Editor:
X. Sharon Hu
University of Notre Dame, USA

Issue’s Table of Contents

Copyright © 2020 ACM.

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Association for Computing Machinery

New York, NY, United States

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ACM Journals for the Design of Smart and Connected Systems

Publication History

Published: 03 August 2020

Online AM: 07 May 2020

Accepted: 01 March 2020

Revised: 01 December 2019

Received: 01 June 2019

Published in TODAES Volume 25, Issue 5

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Cited By

Ruiu PRubattu CAnedda MLagorio APopescu VAmarie NGiusto DFadda M(2024)Edge-to-Cloud Continuum Orchestrator for Distributed Video Applications2024 IEEE International Symposium on Broadband Multimedia Systems and Broadcasting (BMSB)10.1109/BMSB62888.2024.10608304(1-6)Online publication date: 19-Jun-2024
https://doi.org/10.1109/BMSB62888.2024.10608304
Lyu ZShen J(2024)Symbolic-functional representation inference for gate-level power estimationMicroelectronics Journal10.1016/j.mejo.2024.106443154(106443)Online publication date: Dec-2024
https://doi.org/10.1016/j.mejo.2024.106443
Nasser YNassar M(2023)Toward Hardware-Assisted Malware Detection Utilizing Explainable Machine Learning: A SurveyIEEE Access10.1109/ACCESS.2023.333518711(131273-131288)Online publication date: 2023
https://doi.org/10.1109/ACCESS.2023.3335187
Richa MPrévotet JDardaillon MMroué MSamhat A(2023)High-level power estimation techniques in embedded systems hardware: an overviewThe Journal of Supercomputing10.1007/s11227-022-04798-579:4(3771-3790)Online publication date: 1-Mar-2023
https://dl.acm.org/doi/10.1007/s11227-022-04798-5
Richa MPrevotet JDardaillon MMroue MSamhat A(2022)High-Level Early Power Estimation of FPGA IP Based on Machine Learning2022 29th IEEE International Conference on Electronics, Circuits and Systems (ICECS)10.1109/ICECS202256217.2022.9970952(1-4)Online publication date: 24-Oct-2022
https://doi.org/10.1109/ICECS202256217.2022.9970952
Richa MPrevotet JDardaillon MMroue MSamhat A(2022)Automated Training Data Construction using Measurements for High-Level Learning-Based FPGA Power Modeling2022 International Conference on Smart Systems and Power Management (IC2SPM)10.1109/IC2SPM56638.2022.9988835(170-175)Online publication date: 10-Nov-2022
https://doi.org/10.1109/IC2SPM56638.2022.9988835
Nasser YLorandel JPrevotet JHelard M(2021)RTL to Transistor Level Power Modeling and Estimation Techniques for FPGA and ASIC: A SurveyIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2020.300327640:3(479-493)Online publication date: Mar-2021
https://doi.org/10.1109/TCAD.2020.3003276
Govindaraj VArunadevi B(2021)Machine Learning Based Power Estimation for CMOS VLSI CircuitsApplied Artificial Intelligence10.1080/08839514.2021.1966885(1-13)Online publication date: 20-Aug-2021
https://doi.org/10.1080/08839514.2021.1966885

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