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A low-complexity issue logic

Authors:

Antonio GonzálezAuthors Info & Claims

ICS '00: Proceedings of the 14th international conference on Supercomputing

Pages 327 - 335

https://doi.org/10.1145/335231.335263

Published: 08 May 2000 Publication History

Abstract

One of the main concerns in today's processor design is the issue logic. Instruction-level parallelism is usually favored by an out-of-order issue mechanism where instructions can issue independently of the program order. The out-of-order scheme yields the best performance but at the same time introduces important hardware costs such as an associative look-up, which might be prohibitive for wide issue processors with large instruction windows. This associative search may slow-down the clock-rate and it has an important impact on power consumption. In this work, two new issue schemes that reduce the hardware complexity of the issue logic with minimal impact on the average number of instructions executed per cycle are presented.

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A low-complexity issue logic

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Published In

cover image ACM Conferences

ICS '00: Proceedings of the 14th international conference on Supercomputing

May 2000

347 pages

ISBN:1581132700

DOI:10.1145/335231

Chairmen:
John Reynders
Los Alamos National Lab, Los Alamos, NM
,
Alex Veidenbaum
Univ. of California at Irvine, Irvine

Copyright © 2000 ACM.

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Published: 08 May 2000

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ICS00: International Conference on Supercomputing

May 8 - 11, 2000

New Mexico, Santa Fe, USA

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ICS '00 Paper Acceptance Rate 33 of 122 submissions, 27%;

Overall Acceptance Rate 629 of 2,180 submissions, 29%

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https://dl.acm.org/doi/10.1145/3548688
Gao SGao CHe YZeng JNie LXia XLyu M(2023)Code Structure–Guided Transformer for Source Code SummarizationACM Transactions on Software Engineering and Methodology10.1145/352267432:1(1-32)Online publication date: 13-Feb-2023
https://dl.acm.org/doi/10.1145/3522674
Luo WYan ZSong QTan R(2022)Physics-directed Data Augmentation for Deep Model Transfer to Specific SensorACM Transactions on Sensor Networks10.1145/354907619:1(1-30)Online publication date: 8-Dec-2022
https://dl.acm.org/doi/10.1145/3549076
Diavastos ACarlson T(2022)Efficient Instruction Scheduling Using Real-time Load Delay TrackingACM Transactions on Computer Systems10.1145/354868140:1-4(1-21)Online publication date: 24-Nov-2022
https://dl.acm.org/doi/10.1145/3548681
Schwarz A(2022)Robust level-3 BLAS Inverse Iteration from the Hessenberg MatrixACM Transactions on Mathematical Software10.1145/354478948:3(1-30)Online publication date: 10-Sep-2022
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Bingcai SCaixia SYongwen WHui G(2022)Design and optimization of Issue queue in Out-of-Order superscalar microprocessor2022 Asia Conference on Algorithms, Computing and Machine Learning (CACML)10.1109/CACML55074.2022.00056(294-298)Online publication date: Mar-2022
https://doi.org/10.1109/CACML55074.2022.00056
Zhou YYu ZZhang CXu YWang HWang SSun NBao YZhou HMoreira JMueller FEtsion Y(2021)OmegaflowProceedings of the 35th ACM International Conference on Supercomputing10.1145/3447818.3460367(152-163)Online publication date: 3-Jun-2021
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Alipour MKaxiras SBlack-Schaffer DKumar R(2020)Delay and Bypass: Ready and Criticality Aware Instruction Scheduling in Out-of-Order Processors2020 IEEE International Symposium on High Performance Computer Architecture (HPCA)10.1109/HPCA47549.2020.00042(424-434)Online publication date: Feb-2020
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Wong HBetz VRose J(2018)High-Performance Instruction Scheduling Circuits for Superscalar Out-of-Order Soft ProcessorsACM Transactions on Reconfigurable Technology and Systems10.1145/309374111:1(1-22)Online publication date: 9-Jan-2018
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Wong HBetz VRose J(2016)High Performance Instruction Scheduling Circuits for Out-of-Order Soft Processors2016 IEEE 24th Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM)10.1109/FCCM.2016.11(9-16)Online publication date: May-2016
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