research-article

Public Access

Efficient and Reliable Error Detection Architectures of Hash-Counter-Hash Tweakable Enciphering Schemes

Authors:

Mehran Mozaffari-Kermani,

Reza Azarderakhsh,

Ausmita Sarker,

Amir JalaliAuthors Info & Claims

ACM Transactions on Embedded Computing Systems (TECS), Volume 17, Issue 2

Article No.: 54, Pages 1 - 19

https://doi.org/10.1145/3159173

Published: 23 January 2018 Publication History

Abstract

Through pseudorandom permutation, tweakable enciphering schemes (TES) constitute block cipher modes of operation which perform length-preserving computations. The state-of-the-art research has focused on different aspects of TES, including implementations on hardware [field-programmable gate array (FPGA)/ application-specific integrated circuit (ASIC)] and software (hard/soft-core microcontrollers) platforms, algorithmic security, and applicability to sensitive, security-constrained usage models. In this article, we propose efficient approaches for protecting such schemes against natural and malicious faults. Specifically, noting that intelligent attackers do not merely get confined to injecting multiple faults, one major benchmark for the proposed schemes is evaluation toward biased and burst fault models. We evaluate a variant of TES, i.e., the Hash-Counter-Hash scheme, which involves polynomial hashing as other variants are either similar or do not constitute finite field multiplication which, by far, is the most involved operation in TES. In addition, we benchmark the overhead and performance degradation on the ASIC platform. The results of our error injection simulations and ASIC implementations show the suitability of the proposed approaches for a wide range of applications including deeply embedded systems.

References

[1]

P. Ahir, M. Mozaffari Kermani, and R. Azarderakhsh. 2017. Lightweight architectures for reliable and fault detection Simon and Speck cryptographic algorithms on FPGA. ACM Transactions on Embedded Computer Systems 16, 4 (2017), 109:1--109:17.

Digital Library

[2]

S. Bayat-Sarmadi, M. Mozaffari Kermani, and A. Reyhani-Masoleh. 2014. Efficient and concurrent reliable realization of the secure cryptographic SHA-3 algorithm. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 33, 7 (2014), 1105--1109.

[3]

R. Beaulieu, D. Shors, J. Smith, S. T. Clark, B. Weeks, and L. Wingers. 2013. The Simon and Speck families of block ciphers. In Proc. Cryptology ePrint Archive, Report no. 2013/404.

[4]

R. Beaulieu, D. Shors, J. Smith, S. T. Clark, B. Weeks, and L. Wingers. 2015. Simon andSpeck: Block ciphers for the internet of things. In Proc. Cryptology ePrint Archive, Report no. 2015/585.

[5]

D. Bernstein. 2007. Polynomial evaluation and message authentication. Retrieved January 2018 from https://cr.yp.to/antiforgery/pema-20071022.pdf.

[6]

R. Bhaumik and M. Nandi. 2015. An inverse-free single-keyed tweakable enciphering scheme. In Proc. ASIACRYPT. 159--180.

Digital Library

[7]

C. D. Cannière, O. Dunkelman, and M. Knezevic. 2009. KATAN 8 KTANTAN - A family of small and efficient hardware-oriented block ciphers. In Proc. Cryptographic Hardware and Embedded Systems. 272--288.

Digital Library

[8]

D. Chakraborty and P. Sarkar. 2008. HCH: A new tweakable enciphering scheme using the hash-counter-hash approach. IEEE Transactions on Information Theory 54, 4 (2008), 1683--1699.

Digital Library

[9]

D. Chakraborty, C. Mancillas-Lopez, F. Rodriguez-Henriquez, and P. Sarkar. 2013. Efficient hardware implementations of BRW polynomials and tweakable enciphering schemes. IEEE Transactions on Computers 62, 2 (2013), 279--294.

Digital Library

[10]

D. Chakraborty, C. Mancillas-Lopez, and P. Sarkar. 2017. Disk encryption: Do we need to preserve length? Journal of Cryptographic Engineering, 1--21.

[11]

X. Guo and R. Karri. 2013. Recomputing with permuted operands: A concurrent error detection approach. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 32, 10 (2013), 1595--1608.

Digital Library

[12]

X. Guo, D. Mukhopadhyay, C. Jin, and R. Karri. 2015. Security analysis of concurrent error detection against differential fault analysis. Journal on Cryptographic Engineering 5, 3 (2015), 153--169.

[13]

J. Guo, T. Peyrin, A. Poschmann, and M. J. B. Robshaw. 2011. The LED block cipher. In Proc. Cryptographic Hardware and Embedded Systems. 326--341.

Digital Library

[14]

S. Halevi. 2004. EME: Extending EME to handle arbitrary-length messages with as sociated data. In Proc. INDOCRYPT. 315--327.

Digital Library

[15]

S. Halevi. 2007. Invertible universal hashing and the TET encryption mode. In Proc. Advances in Cryptology-Ann. Int. Cryptology Conf. (CRYPTO). 412--429.

Digital Library

[16]

S. Halevi and P. Rogaway. 2003. A tweakable enciphering mode. In Proc. Advances in Cryptology-Ann. Int. Cryptology Conf. (CRYPTO). 482--499.

[17]

S. Halevi and P. Rogaway. 2004. A parallelizable enciphering mode. In Proc. CT-RSA. 292--304.

[18]

IEEE Security in Storage Working Group (SISWG) P1619. 2017. PRP Modes Comparison IEEE p1619. Retrieved May 2017 from http://siswg.net/, IEEE Computer Society.

[19]

D. Karaklajic, J.-M. Schmidt, and I. Verbauwhede. 2013. Hardware designer’s guide to fault attacks. IEEE Transactions on Very Large Scale Integration (VLSI) Systems 21, 12 (2013), 2295--2306.

Digital Library

[20]

M. Liskov, R. L. Rivest, and D. Wagner. 2002. Tweakable block ciphers. In Proc. Advances in Cryptology-Ann. Int. Cryptology Conf. (CRYPTO). 31--46.

Digital Library

[21]

P. Maistri and R. Leveugle. 2008. Double-Data-Rate computation as a countermeasure against fault analysis. IEEE Transactions on Computers 57, 11 (2008), 1528--1539.

Digital Library

[22]

C. Mancillas-Lopez, D. Chakraborty, and F. Rodriguez-Henriquez. 2010. Reconfigurable hardware implementations of tweakable enciphering schemes. IEEE Transactions on Computers 59, 11 (2010), 1547--1561.

Digital Library

[23]

A. Moradi, A. Poschmann, S. Ling, C. Paar, and H. Wang. 2011. Pushing the limits: A very compact and a threshold implementation of AES. In Proc. Advances in Cryptology. 69--88.

Digital Library

[24]

M. Mozaffari-Kermani and A. Reyhani-Masoleh. 2008. A lightweight concurrent fault detection scheme for the AES S-Boxes using normal basis. In Proc. LNCS Cryptographic Hardware and Embedded Systems (CHES). 113--129.

Digital Library

[25]

M. Mozaffari-Kermani and A. Reyhani-Masoleh. 2010. Concurrent structure independent fault detection schemes for the advanced encryption standard. IEEE Transactions on Computers 59, 5 (2010), 608--622.

Digital Library

[26]

M. Mozaffari-Kermani and A. Reyhani-Masoleh. 2012. Efficient and high-performance parallel hardware architectures for the AES-GCM. 2012. IEEE Transactions on Computers 61, 8 (2012), 1165--1178.

Digital Library

[27]

M. Mozaffari-Kermani and R. Azarderakhsh. 2013. Efficient fault diagnosis schemes for reliable lightweight cryptographic ISO/IEC standard CLEFIA benchmarked on ASIC and FPGA. IEEE Transactions on Industrial Electronics 60, 12 (2013), 5925--5932.

[28]

M. Mozaffari-Kermani and R. Azarderakhsh. 2015. Reliable hash trees for post-quantum stateless cryptographic hash-based signatures. In Proc. IEEE Int. Symp. Defect and Fault Tolerance in VLSI Systems (DFT). 103--108.

[29]

M. Mozaffari-Kermani, K. Tian, R. Azarderakhsh, and S. Bayat-Sarmadi. 2014. Fault-resilient lightweight cryptographic block ciphers for secure embedded systems. IEEE Embedded Systems 6, 4 (2014), 89--92.

[30]

M. Mozaffari Kermani, R. Azarderakhsh, and A. Aghaie. 2016. Fault detection architectures for post-quantum cryptographic stateless hash-based secure signatures benchmarked on ASIC. ACM Transactions Embedded Computing Systems 16, 2 (2016), 59:1--59:19.

Digital Library

[31]

G. Di Natale, M. Doulcier, M. L. Flottes, and B. Rouzeyre. 2009. A reliable architecture for parallel implementations of the advanced encryption standard. J. Electronic Testing: Theory and Applications 25, 4 (2009), 269--278.

Digital Library

[32]

T. Peyrin and Y. Seurin. 2016. Counter-in-Tweak: Authenticated encryption modes for tweakable block ciphers. In Proc. Advances in Cryptology. 33-63.

Digital Library

[33]

M. O. Rabin and S. Winograd. 1972. Fast evaluation of polynomials by rational preparation. Communications on Pure and Applied Mathematics 25 (1972), 433--458.

[34]

P. Sarkar. 2009. Tweakable enciphering schemes using only the encryption function of a block cipher. Retrieved January 2018 from https://eprint.iacr.org/2009/216.pdf.

[35]

A. Satoh, T. Sugawara, and T. Aoki. 2009. High-performance hardware architectures for Galois Counter Mode. IEEE Transactions on Computers 58, 7 (2009), 917--930.

Digital Library

[36]

K. Shibutani, T. Isobe, H. Hiwatari, A. Mitsuda, T. Akishita, and T. Shirai. 2011. Piccolo: An ultra-lightweight blockcipher. In Proc. Cryptographic Hardware and Embedded Systems. 342--357.

Digital Library

[37]

F. X. Standaert, G. Piret, N. Gershenfeld, and J. J. Quisquater. 2006. SEA: A scalable encryption algorithm for small embedded applications. In Proc. Smart Card Research and Advanced Applications. 222--236.

Digital Library

[38]

M. Yasin, B. Mazumdar, S. Subidh Ali, and O. Sinanoglu. 2015. Security analysis of logic encryption against the most effective side-channel attack: DPA. In Proc. DFTS. 97--102.

[39]

C. H. Yen and B. F. Wu. 2006. Simple error detection methods for hardware implementation of advanced encryption standard. IEEE Transactions on Computers 55, 6, 720--731.

Digital Library

Cited By

Cintas-Canto AKermani MAzarderakhsh R(2023)Error Detection Constructions for ITA Finite Field Inversions Over $\text{GF}(2^{m})$ on FPGA Using CRC and Hamming CodesIEEE Transactions on Reliability10.1109/TR.2022.321601472:2(651-661)Online publication date: Jun-2023
https://doi.org/10.1109/TR.2022.3216014
Sarker ACanto AMozaffari Kermani MAzarderakhsh R(2023)Error Detection Architectures for Hardware/Software Co-Design Approaches of Number-Theoretic TransformIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2022.321861442:7(2418-2422)Online publication date: Jul-2023
https://doi.org/10.1109/TCAD.2022.3218614
Kaur JKermani MAzarderakhsh R(2022)Hardware Constructions for Lightweight Cryptographic Block Cipher QARMA With Error Detection MechanismsIEEE Transactions on Emerging Topics in Computing10.1109/TETC.2020.302778910:1(514-519)Online publication date: 1-Jan-2022
https://doi.org/10.1109/TETC.2020.3027789
Show More Cited By

Index Terms

Efficient and Reliable Error Detection Architectures of Hash-Counter-Hash Tweakable Enciphering Schemes
1. Hardware
  1. Hardware test
    1. Hardware reliability screening
  2. Very large scale integration design
    1. Application-specific VLSI designs
      1. Application specific integrated circuits

Recommendations

Reconfigurable Hardware Implementations of Tweakable Enciphering Schemes

Tweakable enciphering schemes are length-preserving block cipher modes of operation that provide a strong pseudorandom permutation. It has been suggested that these schemes can be used as the main building blocks for achieving in-place disk encryption. ...
Tweakable enciphering schemes from hash-sum-expansion
INDOCRYPT'07: Proceedings of the cryptology 8th international conference on Progress in cryptology

We study a tweakable blockcipher for arbitrarily long message (also called a tweakable enciphering scheme) that consists of a universal hash function and an expansion, a keyed function with short input and long output. Such schemes, called HCTR and HCH, ...
Efficient implementations of some tweakable enciphering schemes in reconfigurable hardware
INDOCRYPT'07: Proceedings of the cryptology 8th international conference on Progress in cryptology

We present optimized FPGA implementations of three tweak-able enciphering schemes, namely, HCH, HCTR and EME using AES-128 as the underlying block cipher.We report performance timings and hardware resources occupied by these three modes when using a ...

Comments

Please enable JavaScript to view thecomments powered by Disqus.

Information & Contributors

Information

Published In

cover image ACM Transactions on Embedded Computing Systems

ACM Transactions on Embedded Computing Systems Volume 17, Issue 2

Special Issue on MEMCODE 2015 and Regular Papers (Diamonds)

March 2018

640 pages

ISSN:1539-9087

EISSN:1558-3465

DOI:10.1145/3160927

Editor:
Sandeep K. Shukla
Indian Institute of Technology, India

Issue’s Table of Contents

Copyright © 2018 ACM.

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

Publisher

Association for Computing Machinery

New York, NY, United States

Journal Family

ACM Journals for the Design of Smart and Connected Systems

Publication History

Published: 23 January 2018

Accepted: 01 November 2017

Revised: 01 August 2017

Received: 01 May 2017

Published in TECS Volume 17, Issue 2

Permissions

Request permissions for this article.

Request Permissions

Check for updates

Author Tags

Qualifiers

Research-article
Research
Refereed

Funding Sources

U.S. Department of Commerce
National Institute of Standards and Technology (NIST)
U.S. federal agency

Contributors

Other Metrics

View Article Metrics

Bibliometrics & Citations

Bibliometrics

Article Metrics

9
Total Citations
View Citations
240
Total Downloads

Downloads (Last 12 months)60
Downloads (Last 6 weeks)8

Reflects downloads up to 20 Nov 2024

Other Metrics

View Author Metrics

Citations

Cited By

Cintas-Canto AKermani MAzarderakhsh R(2023)Error Detection Constructions for ITA Finite Field Inversions Over $\text{GF}(2^{m})$ on FPGA Using CRC and Hamming CodesIEEE Transactions on Reliability10.1109/TR.2022.321601472:2(651-661)Online publication date: Jun-2023
https://doi.org/10.1109/TR.2022.3216014
Sarker ACanto AMozaffari Kermani MAzarderakhsh R(2023)Error Detection Architectures for Hardware/Software Co-Design Approaches of Number-Theoretic TransformIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2022.321861442:7(2418-2422)Online publication date: Jul-2023
https://doi.org/10.1109/TCAD.2022.3218614
Kaur JKermani MAzarderakhsh R(2022)Hardware Constructions for Lightweight Cryptographic Block Cipher QARMA With Error Detection MechanismsIEEE Transactions on Emerging Topics in Computing10.1109/TETC.2020.302778910:1(514-519)Online publication date: 1-Jan-2022
https://doi.org/10.1109/TETC.2020.3027789
Kaur JMozaffari Kermani MAzarderakhsh R(2022)Hardware Constructions for Error Detection in Lightweight Authenticated Cipher ASCON Benchmarked on FPGAIEEE Transactions on Circuits and Systems II: Express Briefs10.1109/TCSII.2021.313646369:4(2276-2280)Online publication date: Apr-2022
https://doi.org/10.1109/TCSII.2021.3136463
Cintas-Canto AMozaffari-Kermani MAzarderakhsh RGaj K(2022)CRC-Oriented Error Detection Architectures of Post-quantum Cryptography Niederreiter Key Generator on FPGA2022 IEEE Nordic Circuits and Systems Conference (NorCAS)10.1109/NorCAS57515.2022.9934378(1-7)Online publication date: 25-Oct-2022
https://doi.org/10.1109/NorCAS57515.2022.9934378
Canto AMozaffari-Kermani MAzarderakhsh R(2021)Reliable CRC-Based Error Detection Constructions for Finite Field Multipliers With Applications in CryptographyIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2020.303117029:1(232-236)Online publication date: Jan-2021
https://doi.org/10.1109/TVLSI.2020.3031170
Cintas Canto AKermani MAzarderakhsh R(2021)Reliable Architectures for Composite-Field-Oriented Constructions of McEliece Post-Quantum Cryptography on FPGAIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2020.301998740:5(999-1003)Online publication date: May-2021
https://doi.org/10.1109/TCAD.2020.3019987
Sarker AMozaffari-Kermani MAzarderakhsh R(2019)Hardware Constructions for Error Detection of Number-Theoretic Transform Utilized in Secure Cryptographic ArchitecturesIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2018.288109727:3(738-741)Online publication date: Mar-2019
https://doi.org/10.1109/TVLSI.2018.2881097
Kermani MBayat-Sarmadi SAckie AAzarderakhsh R(2019)High-Performance Fault Diagnosis Schemes for Efficient Hash Algorithm BLAKE2019 IEEE 10th Latin American Symposium on Circuits & Systems (LASCAS)10.1109/LASCAS.2019.8667597(201-204)Online publication date: Feb-2019
https://doi.org/10.1109/LASCAS.2019.8667597

View Options

View options

PDF

View or Download as a PDF file.

eReader

View online with eReader.

Login options

Check if you have access through your login credentials or your institution to get full access on this article.

Full Access

Get this Article

Media

Figures

Other

Tables

View Issue’s Table of Contents