research-article

Using Criticality of GPU Accesses in Memory Management for CPU-GPU Heterogeneous Multi-Core Processors

Authors:

Mainak ChaudhuriAuthors Info & Claims

ACM Transactions on Embedded Computing Systems (TECS), Volume 16, Issue 5s

Article No.: 133, Pages 1 - 23

https://doi.org/10.1145/3126540

Published: 27 September 2017 Publication History

Abstract

Heterogeneous chip-multiprocessors with CPU and GPU integrated on the same die allow sharing of critical memory system resources among the CPU and GPU applications. Such architectures give rise to challenging resource scheduling problems. In this paper, we explore memory access scheduling algorithms driven by criticality of GPU accesses in such systems. Different GPU access streams originate from different parts of the GPU rendering pipeline, which behaves very differently from the typical CPU pipeline requiring new techniques for GPU access criticality estimation. We propose a novel queuing network model to estimate the performance-criticality of the GPU access streams. If a GPU application performs below the quality of service requirement (e.g., frame rate in 3D scene rendering), the memory access scheduler uses the estimated criticality information to accelerate the critical GPU accesses. Detailed simulations done on a heterogeneous chip-multiprocessor model with one GPU and four CPU cores running heterogeneous mixes of DirectX, OpenGL, and CPU applications show that our proposal improves the GPU performance by 15% on average without degrading the CPU performance much. Extensions proposed for the mixes containing GPGPU applications, which do not have any quality of service requirement, improve the performance by 7% on average for these mixes.

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Fang JLin SYang HXu YSu X(2023)A perceptual and predictive batch-processing memory scheduling strategy for a CPU-GPU heterogeneous systemCPU-GPU异构系统感知和预测的批处理内存调度策略Frontiers of Information Technology & Electronic Engineering10.1631/FITEE.220044924:7(994-1006)Online publication date: 28-Jul-2023
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Agarwal SChakraborty SSjälander M(2023)Architecting Selective Refresh based Multi-Retention Cache for Heterogeneous System (ARMOUR)2023 60th ACM/IEEE Design Automation Conference (DAC)10.1109/DAC56929.2023.10247878(1-6)Online publication date: 9-Jul-2023
https://doi.org/10.1109/DAC56929.2023.10247878
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Index Terms

Using Criticality of GPU Accesses in Memory Management for CPU-GPU Heterogeneous Multi-Core Processors
1. Computer systems organization
  1. Architectures
    1. Other architectures
      1. Heterogeneous (hybrid) systems

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Published In

cover image ACM Transactions on Embedded Computing Systems

ACM Transactions on Embedded Computing Systems Volume 16, Issue 5s

Special Issue ESWEEK 2017, CASES 2017, CODES + ISSS 2017 and EMSOFT 2017

October 2017

1448 pages

ISSN:1539-9087

EISSN:1558-3465

DOI:10.1145/3145508

Editor:
Sandeep K. Shukla
Indian Institute of Technology, India

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Copyright © 2017 ACM.

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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ACM Journals for the Design of Smart and Connected Systems

Publication History

Published: 27 September 2017

Accepted: 01 June 2017

Revised: 01 June 2017

Received: 01 April 2017

Published in TECS Volume 16, Issue 5s

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Fang JLin SYang HXu YSu X(2023)A perceptual and predictive batch-processing memory scheduling strategy for a CPU-GPU heterogeneous systemCPU-GPU异构系统感知和预测的批处理内存调度策略Frontiers of Information Technology & Electronic Engineering10.1631/FITEE.220044924:7(994-1006)Online publication date: 28-Jul-2023
https://doi.org/10.1631/FITEE.2200449
Agarwal SChakraborty SSjälander M(2023)Architecting Selective Refresh based Multi-Retention Cache for Heterogeneous System (ARMOUR)2023 60th ACM/IEEE Design Automation Conference (DAC)10.1109/DAC56929.2023.10247878(1-6)Online publication date: 9-Jul-2023
https://doi.org/10.1109/DAC56929.2023.10247878
Zeng QDu YHuang KLeung K(2021)Energy-Efficient Resource Management for Federated Edge Learning With CPU-GPU Heterogeneous ComputingIEEE Transactions on Wireless Communications10.1109/TWC.2021.308891020:12(7947-7962)Online publication date: Dec-2021
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Singh ABasireddy KPrakash AMerrett GAl-Hashimi B(2019)Collaborative Adaptation for Energy-Efficient Heterogeneous Mobile SoCsIEEE Transactions on Computers10.1109/TC.2019.2943855(1-1)Online publication date: 2019
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Kim JShin PNoh SHam DHong S(2018)Reducing Memory Interference Latency of Safety-Critical Applications via Memory Request Throttling and Linux Cgroup2018 31st IEEE International System-on-Chip Conference (SOCC)10.1109/SOCC.2018.8618555(215-220)Online publication date: Sep-2018
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He XChen Y(2018)Deadline-aware Memory Scheduler and Governor for Heterogeneous Processors2018 IEEE 16th International Conference on Industrial Informatics (INDIN)10.1109/INDIN.2018.8471962(239-244)Online publication date: Jul-2018
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