Article

Free access

ENOR: model order reduction of RLC circuits using nodal equations for efficient factorization

Author:

Bernard N. SheehanAuthors Info & Claims

DAC '99: Proceedings of the 36th annual ACM/IEEE Design Automation Conference

Pages 17 - 21

https://doi.org/10.1145/309847.309855

Published: 01 June 1999 Publication History

PDF eReader

References

[1]

A. Odabasioglu, M. Celik, L. T. Pileggi, "PRIMA: Passive Reduced-order Interconnect Macromodeling Algorithm," 34th DAC, pp. 58-65, 1997

Digital Library

Google Scholar

[2]

L. Rohrer and L. Pillage, "Asymptotic Waveform Evaluation for Timing Analysis," IEEE Trans. Computer Aided Design, vol. 9, pp. 352-66, 1990.

Crossref

Google Scholar

[3]

P. Feldmann and R. W. Freund, "Reduced-Order Modeling of Large Linear Subcircuits via a Block Lanczos Algorithm," 32nd DAC, pp. 474-79, 1995.

Digital Library

Google Scholar

[4]

M. Silveira, M. Kamon, I. Elfadel and J. White, "A Coordinate-Transformed Arnoldi Algorithm for Generating Guaranteed Stable Reduced-Order Models of RLC Circuits," 33rd DAC, pp. 288-94, 1996.

Digital Library

Google Scholar

[5]

K. Kerns, I. Wemple, A. Yang, "Stable and Efficient Reduction of Substrate Model Networks Using Congruence Transforms," ICCAD 1995, pp. 207-14.

Digital Library

Google Scholar

[6]

R. W. Freund and P. Feldmann, "Reduced-Order Modelling of Large Passive Linear Circuits by Means of the SyPVL Algorithm," 33rd DAC, pp. 280-87, 1996.

Digital Library

Google Scholar

[7]

K. L. Shepard, V. Narayanan, P. C. Elmendorf, G. Zheng, "Global Harmony: Coupled Noise Analysis for Full-Chip RC Interconnect Networks", 34th DAC, pp. 139-46, 1997.

Digital Library

Google Scholar

[8]

B. Sheehan, "Projective Convolution: RLC Model- Order Reduction Using the Impulse Response", DATE 99, 1999.

Digital Library

Google Scholar

[9]

C. Ratzlaff and L. Pillage, "RICE: Rapid Interconnect Circuit Evaluation Using AWE," IEEE Trans. CAD, vol. 13, pp. 763-76, 1994.

Digital Library

Google Scholar

[10]

A. George and J. W-H Liu. Computer Solution of Large Sparse Positive Definite Systems. Prentice-Hall, New Jersey, 1981.

Digital Library

Google Scholar

[11]

E. A. Guillemin, Synthesis of Passive Networks, John Wiley and Sons, 1957.

Google Scholar

Cited By

View all

Hao LShi G(2023)Realizable Reduction of Multi-Port RCL Networks by Block EliminationIEEE Transactions on Circuits and Systems I: Regular Papers10.1109/TCSI.2022.321854870:1(399-412)Online publication date: Jan-2023
https://doi.org/10.1109/TCSI.2022.3218548
Fotyga G(2022)Study of the Effectiveness of Model Order Reduction Algorithms in the Finite Element Method Analysis of Multi-port Microwave Structures2022 24th International Microwave and Radar Conference (MIKON)10.23919/MIKON54314.2022.9924948(1-3)Online publication date: 12-Sep-2022
https://doi.org/10.23919/MIKON54314.2022.9924948
Fotyga GSzypulski DLamecki ASypek PRewienski Mde la Rubia VMrozowski M(2022)An MOR Algorithm Based on the Immittance Zero and Pole Eigenvectors for Fast FEM Simulations of Two-Port Microwave StructuresIEEE Transactions on Microwave Theory and Techniques10.1109/TMTT.2022.316665770:6(2979-2988)Online publication date: Jun-2022
https://doi.org/10.1109/TMTT.2022.3166657
Show More Cited By

Index Terms

ENOR: model order reduction of RLC circuits using nodal equations for efficient factorization
1. Hardware
  1. Robustness

Recommendations

Analysis of power-performance for ultra-thin-body GeOI logic circuits
ISLPED '11: Proceedings of the 17th IEEE/ACM international symposium on Low-power electronics and design

This work analyzes the power-performance of the emerging Ultra-Thin-Body (UTB) GeOI devices for logic circuit applications. The impacts of temperature and Vdd scaling on the leakage/delay are studied. Compared with the subthreshold leakage dominated SOI ...
Impact of channel length, gate insulator thickness, gate insulator material, and temperature on the performance of nanoscale FETs

Aggressive technology scaling as per Moore's law has led to elevated power dissipation levels owing to an exponential increase in subthreshold leakage power. Short channel effects (SCEs) due to channel length reduction, gate insulator thickness change, ...
3-D analytical modeling of high-k gate stack dual-material tri-gate strained silicon-on-nothing MOSFET with dual-material bottom gate for suppressing short channel effects

This paper presents a detailed study of the response of a new structure namely, high-k gate stack dual-material tri-gate strained silicon-on-nothing MOSFET with dual material bottom gate, towards various short channel effects, namely, drain-induced ...

Comments

Please enable JavaScript to view thecomments powered by Disqus.

Information & Contributors

Information

Published In

DAC '99: Proceedings of the 36th annual ACM/IEEE Design Automation Conference

June 1999

1000 pages

ISBN:1581131097

DOI:10.1145/309847

Editor:
Mary Jane Irwin

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

Publisher

Association for Computing Machinery

New York, NY, United States

Publication History

Published: 01 June 1999

Permissions

Request permissions for this article.

Request Permissions

Check for updates

Qualifiers

Article

Conference

DAC99

Sponsor:

EDAC
SIGDA
IEEE-CAS

DAC99: The 36th ACM/IEEE-CAS/EDAC Design Automation Conference

June 21 - 25, 1999

Louisiana, New Orleans, USA

Acceptance Rates

DAC '99 Paper Acceptance Rate 154 of 451 submissions, 34%;

Overall Acceptance Rate 1,770 of 5,499 submissions, 32%

Upcoming Conference

DAC '25

Sponsor:
sigda

62nd ACM/IEEE Design Automation Conference

June 22 - 26, 2025

San Francisco , CA , USA

Contributors

Other Metrics

View Article Metrics

Bibliometrics & Citations

Bibliometrics

Article Metrics

77
Total Citations
View Citations
596
Total Downloads

Downloads (Last 12 months)95
Downloads (Last 6 weeks)19

Reflects downloads up to 12 Nov 2024

Other Metrics

View Author Metrics

Citations

Cited By

View all

Hao LShi G(2023)Realizable Reduction of Multi-Port RCL Networks by Block EliminationIEEE Transactions on Circuits and Systems I: Regular Papers10.1109/TCSI.2022.321854870:1(399-412)Online publication date: Jan-2023
https://doi.org/10.1109/TCSI.2022.3218548
Fotyga G(2022)Study of the Effectiveness of Model Order Reduction Algorithms in the Finite Element Method Analysis of Multi-port Microwave Structures2022 24th International Microwave and Radar Conference (MIKON)10.23919/MIKON54314.2022.9924948(1-3)Online publication date: 12-Sep-2022
https://doi.org/10.23919/MIKON54314.2022.9924948
Fotyga GSzypulski DLamecki ASypek PRewienski Mde la Rubia VMrozowski M(2022)An MOR Algorithm Based on the Immittance Zero and Pole Eigenvectors for Fast FEM Simulations of Two-Port Microwave StructuresIEEE Transactions on Microwave Theory and Techniques10.1109/TMTT.2022.316665770:6(2979-2988)Online publication date: Jun-2022
https://doi.org/10.1109/TMTT.2022.3166657
Tognazzi STribastone MTschaikowski MVandin A(2022)Differential Equivalence for Linear Differential Algebraic EquationsIEEE Transactions on Automatic Control10.1109/TAC.2021.310853067:7(3484-3493)Online publication date: Jul-2022
https://doi.org/10.1109/TAC.2021.3108530
Malik RAlam MMuhammad SDuraihem FMassoud Y(2022)Second-Order Arnoldi Reduction Using Weighted Gaussian KernelIEEE Access10.1109/ACCESS.2022.316773210(41362-41370)Online publication date: 2022
https://doi.org/10.1109/ACCESS.2022.3167732
Zhang XChen HChen J(2021)RGA-SOBAR: Second-Order Block Arnoldi Method Based on Relative Gain Array for Model Order Reduction of MIMO RCS Circuits2021 60th IEEE Conference on Decision and Control (CDC)10.1109/CDC45484.2021.9683464(6908-6913)Online publication date: 14-Dec-2021
https://doi.org/10.1109/CDC45484.2021.9683464
Fotyga G(2021)A Model-Order Reduction Approach for Electromagnetic Problems With Nonaffine Frequency DependenceIEEE Access10.1109/ACCESS.2021.30689379(47481-47490)Online publication date: 2021
https://doi.org/10.1109/ACCESS.2021.3068937
Szypulski DFotyga Gde la Rubia VMrozowski M(2020)A Subspace-Splitting Moment-Matching Model-Order Reduction Technique for Fast Wideband FEM Simulations of Microwave StructuresIEEE Transactions on Microwave Theory and Techniques10.1109/TMTT.2020.300162768:8(3229-3241)Online publication date: Aug-2020
https://doi.org/10.1109/TMTT.2020.3001627
Chen JHu SQiang ZYang SRen Z(2020)A Broadband Enhanced Nodal-Order Reduction Methodology for Large-Scale Equation Sets of 3-D Transient Field ProblemsIEEE Transactions on Magnetics10.1109/TMAG.2019.295307956:3(1-4)Online publication date: Mar-2020
https://doi.org/10.1109/TMAG.2019.2953079
Fotyga GSzypulski DLech RKowalczyk P(2020)Communication Model Order Reduction in Hybrid Methods Involving Generalized Impedance MatrixIEEE Transactions on Antennas and Propagation10.1109/TAP.2020.2970027(1-1)Online publication date: 2020
https://doi.org/10.1109/TAP.2020.2970027
Show More Cited By

View Options

View options

PDF

View or Download as a PDF file.

PDF

eReader

View online with eReader.

eReader

Get Access

Login options

Check if you have access through your login credentials or your institution to get full access on this article.

Cited By

Index Terms

Recommendations

Analysis of power-performance for ultra-thin-body GeOI logic circuits

Impact of channel length, gate insulator thickness, gate insulator material, and temperature on the performance of nanoscale FETs

3-D analytical modeling of high-k gate stack dual-material tri-gate strained silicon-on-nothing MOSFET with dual-material bottom gate for suppressing short channel effects