Article

Test volume and application time reduction through scan chain concealment

Authors:

Ismet Bayraktaroglu,

Alex OrailogluAuthors Info & Claims

DAC '01: Proceedings of the 38th annual Design Automation Conference

Pages 151 - 155

https://doi.org/10.1145/378239.378388

Published: 22 June 2001 Publication History

Abstract

A test pattern compression scheme is proposed in order to reduce test data volume and application time. The number of scan chains that can be supported by an ATE is significantly increased by utilizing an on-chip decompressor. The functionality of the ATE is kept intact by moving the decompression task to the circuit under test. While the number of virtual scan chains visible to the ATE is kept small, the number of internal scan chains driven by the decompressed pattern sequence can be sinificantly increased.

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Cited By

Lee YJang SKang S(2023)Shift Left Quality Management System (QMS) Using a 3-D Matrix Scanning Method on System on a ChipIEEE Transactions on Circuits and Systems II: Express Briefs10.1109/TCSII.2022.321634670:4(1580-1584)Online publication date: Apr-2023
https://doi.org/10.1109/TCSII.2022.3216346
Huang YMilewski SRajski JTyszer JWang C(2020)Low Cost Hypercompression of Test DataIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2019.294576039:10(2964-2975)Online publication date: Oct-2020
https://doi.org/10.1109/TCAD.2019.2945760
Kwon SLee DKim BKapoor PPark BWei G(2020)Structured Compression by Weight Encryption for Unstructured Pruning and Quantization2020 IEEE/CVF Conference on Computer Vision and Pattern Recognition (CVPR)10.1109/CVPR42600.2020.00198(1906-1915)Online publication date: Jun-2020
https://doi.org/10.1109/CVPR42600.2020.00198
Show More Cited By

Index Terms

Test volume and application time reduction through scan chain concealment
1. Applied computing
  1. Physical sciences and engineering
    1. Electronics
    2. Engineering
2. Hardware
  1. Emerging technologies
  2. Robustness

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cover image ACM Conferences

DAC '01: Proceedings of the 38th annual Design Automation Conference

June 2001

863 pages

ISBN:1581132972

DOI:10.1145/378239

Chairman:
Jan Rabaey
Univ. of California

Copyright © 2001 ACM.

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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EDAC: Electronic Design Automation Consortium
SIGDA: ACM Special Interest Group on Design Automation
IEEE-CAS: Circuits & Systems

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Published: 22 June 2001

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Citations

Cited By

Lee YJang SKang S(2023)Shift Left Quality Management System (QMS) Using a 3-D Matrix Scanning Method on System on a ChipIEEE Transactions on Circuits and Systems II: Express Briefs10.1109/TCSII.2022.321634670:4(1580-1584)Online publication date: Apr-2023
https://doi.org/10.1109/TCSII.2022.3216346
Huang YMilewski SRajski JTyszer JWang C(2020)Low Cost Hypercompression of Test DataIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2019.294576039:10(2964-2975)Online publication date: Oct-2020
https://doi.org/10.1109/TCAD.2019.2945760
Kwon SLee DKim BKapoor PPark BWei G(2020)Structured Compression by Weight Encryption for Unstructured Pruning and Quantization2020 IEEE/CVF Conference on Computer Vision and Pattern Recognition (CVPR)10.1109/CVPR42600.2020.00198(1906-1915)Online publication date: Jun-2020
https://doi.org/10.1109/CVPR42600.2020.00198
Yasin MSinanoglu ORajendran J(2017)Testing the Trustworthiness of IC Testing: An Oracle-Less Attack on IC CamouflagingIEEE Transactions on Information Forensics and Security10.1109/TIFS.2017.271095412:11(2668-2682)Online publication date: Nov-2017
https://doi.org/10.1109/TIFS.2017.2710954
Koenemann BKeller B(2016)Design-for-TestElectronic Design Automation for IC System Design, Verification, and Testing10.1201/b19569-27(517-558)Online publication date: 14-Apr-2016
https://doi.org/10.1201/b19569-27
Gębala MMrugalski GMukherjee NRajski JTyszer J(2014)On Using Implied Values in EDT-based Test CompressionProceedings of the 51st Annual Design Automation Conference10.1145/2593069.2593173(1-6)Online publication date: 1-Jun-2014
https://dl.acm.org/doi/10.1145/2593069.2593173
Sakrappanavar PYellampalli SKothari A(2014)Comparative analysis of scan compression techniques2014 International Conference on Electronics, Communication and Computational Engineering (ICECCE)10.1109/ICECCE.2014.7086632(40-44)Online publication date: Nov-2014
https://doi.org/10.1109/ICECCE.2014.7086632
Immareddy STalusani S(2014)Multi level huffman test data compression with multiple scan chain methodInternational Conference on Computing and Communication Technologies10.1109/ICCCT2.2014.7066738(1-6)Online publication date: Dec-2014
https://doi.org/10.1109/ICCCT2.2014.7066738
Lin XKassab MRajski J(2014)Using dynamic shift to reduce test data volume in high-compression designs2014 19th IEEE European Test Symposium (ETS)10.1109/ETS.2014.6847822(1-6)Online publication date: May-2014
https://doi.org/10.1109/ETS.2014.6847822
Sivanantham SPadmavathy MGopakumar GMallick PPerinbam J(2014)Enhancement of test data compression with multistage encodingIntegration10.1016/j.vlsi.2013.12.00147:4(499-509)Online publication date: Sep-2014
https://doi.org/10.1016/j.vlsi.2013.12.001
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