A Review of Techniques for Ageing Detection and Monitoring on Embedded Systems

Silicon manufacturers encounter more challenges as they explore new miniaturized transistor technologies. Efforts to further reduce device footprints prompted moving from planar to three-dimensional (3D) topologies, such as FinFETs and gate-all-around FETs (GAAFETs). This trend continues with vertical GAAFETs featuring vertical nanowires, which are predicted for usage beyond the 5 nm scale [121]. These devices are susceptible to self-heating because the thermal paths to the ambient environment in their complex 3D structures are constrained. An increase in operating temperature accelerates ageing processes and can reduce performance [24]. Additionally, the reduction in size has not been proportionally followed by a lowered operational voltage, causing stronger electric fields applied to the devices.

Next, we describe the main ageing mechanisms that impact Metal-Oxide-Semiconductor Field-Effect Transistors (MOSFETs), the base for all current CMOS technologies, including newer technologies such as FinFETs.

The research for the presented literature comprised consulting various notable scientific databases (IEEE, ACM, Scopus, and Google Scholar) while limiting the results with keywords including ag(e)ing, degradation, failure, monitoring, and the components of interest: FPGA, microcontroller, SoC, and power supply. We excluded, however, board-level mechanical wear-out effects, such as broken interconnects or the degradation of solder joints. Upon the initial searches, we followed the related work referenced by the results. References were selected with the objective of maximizing the variety of detection and monitoring approaches. We did not include work on the design of special ageing hardware probes for ASICs. Instead, we focused on techniques applied to COTS devices without built-in on-chip ageing sensors. The presented techniques have been implemented in real hardware; therefore, their results are empirical and not exclusively based on simulations. This literature compendium includes methods originally designed to assess the system health status while on service as well as methods that have been employed to study the impact of ageing processes on devices under controlled environments.

We consider that the selected components represent well the minimal building blocks present in most modern embedded systems: a main processing unit, memory, and a power source [81]. While a huge variety of peripherals, such as sensors and actuators, are frequently required on certain embedded system domains (e.g., cyber-physical systems and IoT [46]), they are use-case specific in nature and can vary fundamentally in their functioning principles. We aim to abstract from particular deployment cases for embedded devices. Instead, we aspire for this survey to serve as a comprehensive guide across embedded domains and, thus, focus on the body of work concerning FPGAs, MCUs, SoCs, and power supplies.

Given the wide variety of tests that can be performed on the systems under consideration, possible classifications vary depending on the intended use case. In this work, we adapted the classification system proposed by Kochte and Wunderlich [65] and extended it as presented in Figure 5.

The primary variable is the highest testing frequency that each technique can potentially achieve. The classification distinguishes between infrequent testing that requires a system shutdown or special testing equipment, i.e., offline testing, and testing that can be performed autonomously onboard, i.e., online testing or self-testing. Online testing can either be concurrent or non-concurrent depending on whether it runs without influencing the system operation.

Considering the criteria described in Section 3.1 and the taxonomy introduced in Section 3.2, relevant literature has been selected, reviewed, and classified. Table 1 summarizes this related work, which is discussed in detail in the following sections.

Approaches are organized by component: FPGA, Microcontroller Unit (MCU) and SoC, and Low Drop-Out (LDO) and Switching-Mode Power Supply (SMPS). Contributions are further grouped according to their sensing principle. Within each group, references are chronologically ordered so that the latest appear at the end. For each publication, we indicate whether the technique was developed as an online concurrent, online non-concurrent, or offline test. We expose whether techniques were evaluated under aged conditions, whether machine learning (ML) techniques were applied, and whether an analytical or empirical model was developed to study the degradation process.

At first glance, Table 1 reveals that most of the literature focusing on FPGAs proposes online test approaches, whereas related work on MCUs, SoCs, or power supplies dominantly relies on offline tests using external equipment. While various publications in the field of FPGAs and power supplies develop analytical and empirical models of the ageing mechanisms at play, this is not the case for MCUs and SoCs. In FPGA studies, ring oscillators are the preferred technique for characterizing and modelling. Finally, we can also observe a trend towards the application of ML in recent years, mainly for ageing detection techniques.

By observing the intersections of categories, we can further characterize the state-of-the-art. The UpSet plot [73] in Figure 6 shows the various shares of publications that fit into one or several classification categories. Even though 70% of the techniques are based on online tests, this number reduces to 27% if we restrict to those evaluated under accelerated ageing conditions, of which more than half apply to FPGAs. This differs for techniques describing offline tests, of which more than 85% are tested using accelerated ageing. Notably, more than 57% of the techniques that involve ML models require offline tests to work.

The flexibility of FPGAs enables the implementation of monitoring techniques directly on the programmable hardware. Ring Oscillators (ROs), which consist of an odd number of inverters connected in a ring, are one of the most common approaches to measuring digital signal propagation time. RO-based sensors are usually composed of an RO and a frequency-measuring circuit (Figure 7). The frequency at the output of an RO depends —at a given temperature and voltage — on the inverter propagation times \(t_p\) and the number of gates n, as shown in Equation (6).

Zick and Hayes [129] proposed an online concurrent sensing method to measure variations in physical parameters. By using an enhanced RO, an efficient counter, and control logic, the authors developed a compact sensor requiring only 8 Look-Up Tables (LUTs). A residue number system ring counter was implemented, as it requires fewer resources than a binary counter. The temperature sensitivity of the RO was increased to detect hotspots on the chip. RO sensors were placed regularly on a hexagonal tessellation all over the FPGA, together with a softcore, a timer, and a Universal Asynchronous Receiver/Transmitter (UART). The authors measured propagation times and indirectly estimated a transistor current leakage profile, and localized dynamic power usage and temperature.

Sedcole and Cheung [107] placed ROs in a matrix configuration to measure within-die delay variability. The structure enabled the encoding of regions under test into columns and rows. In such a dense configuration, ROs should only be active for short periods of time to avoid heating neighbouring sensors. A single counter, timer, and unified control logic performed the measurements. Pfeifer and Pliva characterized chip delays during design time [95] and analysed the limitations of 28 nm FPGAs [96] with ROs. To measure the oscillations, they implemented a method based on Block RAM (BRAM), which was later formalized in an approach called “Reliability-on-Chip” [93]. The approach requires a true-dual-port BRAM on the chip to undersample the oscillator outputs and a softcore to read the signal streams for calculating the delays. Li et al. [76] not only studied the process variability of 28 nm FPGAs under NBTI by deploying ROs but also utilized the data extracted from accelerated ageing to train various ML models. By building datasets with information regarding the artificial ageing stress conditions and the RO sensor configurations, they found that the XGBoost model performed best across all conditions.

Lanzieri et al. [69] developed an RO measurement module to perform a large-scale study of the propagation delay on 298 Xilinx Virtex-6 devices, which have been naturally aged and in operation as part of a linear particle accelerator. By comparing delay measurements of used and unused devices, the authors found evidence of effects caused by ageing mechanisms. Moreover, an analysis of the radiation exposure of the devices inside the accelerator showed that slower propagation delays are correlated to higher radiation doses.

The application of ROs as variability sensors extends to more modern node technologies as well. Maragos et al. [79] explored increased intra- and inter-die variability on 16 nm FinFET FPGAs with various ROs controlled by an embedded Cortex-A53 CPU. After an ageing process of 8,000 h, Sobas and Marc [111] measured the degradation of various 16 nm FinFET FPGAs by implementing an RO-based test bench. The authors evaluated the effects of static and dynamic stress, and derived an empirical degradation model for both modes that yields estimations with less than 10% relative error. When comparing their results to similar evaluations on 28 nm MOSFETs, they found that the smaller nodes show better reliability on static stress and that BTI was the predominant ageing mechanism (as opposed to HCI). A similar conclusion was reached by Bender et al. [12] from assessing 16 nm FinFET Xilinx devices with a multi-temperature operational life testing method. By evaluating the impact of different temperatures, voltages, frequencies, and RO sizes, the authors managed to isolate the effects of various degradation mechanisms. Additionally, their results suggest that there is a contribution from the self-heating effect to BTI due to the lower heat dissipation of the transistor fins.

Naouss and Marc [85] proposed a test bench to self-characterize the delay of LUTs. Their design allows stress signals to be injected into the Circuit Under Test (CUT) to produce accelerated ageing. This feature was later used to independently study BTI [87] and HCI [86] impact by using different stress signals. They implemented a frequency measuring circuit using three asynchronous counters (one of N bits and two of K bits) and a clock reference. This circuit (Figure 8) allowed for counting the number of cycles in a given period of time as well as the duty cycle of the signal. An enable signal activated the counters and controlled the counting window. Counter A registered the number of cycles of the RO output signal, which was used to calculate the oscillation frequency. Counter B counted the number of clock cycles during the active time of the RO signal, from which the duty cycle was calculated. Measuring the signal duty cycle allowed for studying the impact of ageing on the rising and falling times.

ROs have been employed in offline tests as well [4, 6, 21, 103]. Ahmed et al. [4] used performance degradation to detect recycled FPGAs by exhaustively fingerprinting LUT delays. They synthesized ROs with routes configurable via SRAM. External equipment was used to control the test logic and read out the frequency of each oscillator. Ruffoni and Bogliolo [103] focused on measuring delays of the internal FPGA wires. Two ROs were used, of which one included the wire structure under test. By comparing oscillation frequencies, the delay of the wire was derived. Although the authors employed external equipment, they argued that their method could potentially be operated solely on the device under test. Bruguier et al. [21] proposed a non-invasive method to characterize FPGA performance, analysing the spectra of electromagnetic radiation caused by the ROs. A similar measurement approach was used by Amouri et al. [6] to explore the impact of elevated temperatures and voltages on the performance degradation of FPGAs.

Discussion. RO sensors are relatively easy to implement and very versatile considering that they can provide insights into the effects of BTI and HCI when combined with methods such as multi-temperature operational life testing [12]. Additionally, they can be tuned to indirectly measure other quantities beyond the propagation delay [129]. Although the main sensing principle among approaches is similar, the literature presents multiple approaches to placing the sensors and counting the frequency. A trade-off exists with RO sensors: longer ring chains cover larger areas and require fewer measurement circuits but decrease sensor resolution. Care should be taken to avoid overheating the die or stress power rails by using too few stages in the rings, as this results in unrealistic measurements [95]. A downside of ROs is that they measure delays of the FPGA resources that form the ring and not of the synthesized circuits, which may differ depending on the position and routing. Other techniques measure delays of the existing combinational logic instead, as we describe in the following sections.

The usage of Shadow Registers (SRs) is a well-studied technique for delay characterization and degradation monitoring. Sensors are usually placed at the end of critical combinational paths in parallel to a destination register for detecting late transitions.

Li and Lach [75], Valdés et al. [120], and Leong et al. [72] proposed to place an SR after the CUT that is clocked by a signal skewed from the destination register (Figure 9). By comparing the latched value on both registers and controlling the phase difference of the clock signals, they determine the delay of the CUT. Li and Lach [75] varied the phase difference in runtime to characterize the FPGA propagation delay and built a histogram. Leong et al. [72] implemented an online concurrent ageing monitoring sensor, which detected when the propagation delay was higher than a predefined threshold. Valdés et al. [120] included an on/off signal to their concurrent sensor that interrupts the clock, enabling authors to differentiate the type of ageing mostly suffered by the sensor itself: static ageing (continuous monitoring) or dynamic ageing (periodic monitoring). The sensor functionality was initially tested by operating the circuit under different power supply voltages, which induced a change in its signal propagation delays but did not affect the sensor. The sensor from Valdés et al. was then validated [119] by performing an accelerated ageing process on an FPGA.

The authors reported no significant frequency variations of the clocks on which the sensor reliability depended after the burn-in process. Leong et al. [72] tested sensors by increasing the FPGA frequency and reducing the gap time.

Ghaderi et al. [37] proposed ageing monitors clocked by a single “sensor clock,” which set the maximum allowed slack for combinational signals of critical paths. By injecting the CUT signal and a shifted version of it to an XOR, a positive pulse was generated on each transition of the CUT. The XOR was latched by a Flip-Flop (FF) and triggered by the sensor clock, thereby detecting invalid transitions whenever the pulse occurred too late.

Pfeifer and Pliva [94] presented an online concurrent delay-fault detection technique for combinatorial circuits. The authors used the D FFs at the input of on-chip BRAMs as SRs, which map the signals to memory rows for later analysis. The interconnect introduced a fixed delay between the destination and the SR to control the sensor sensitivity, and an on-board CPU performed the signal comparison.

Wong et al. [123] presented a self-characterization method, with two registers around a combinational CUT, clocked in counter-phase. An XOR between the CUT output and the SR latched value produced the error signal. Transitions occurring after the first half of the test clock period were invalid. The authors leveraged on-chip clock generation to sweep the test clock frequency until the maximum was found. A non-concurrent circuit for start-up tests was also proposed and optimized in [125], which stored test results of each region on the FPGA RAM.

Amouri and Tahoori [7] implemented an ageing sensor to detect late transitions of combinational paths on a Virtex-5 FPGA. The sensor, illustrated in Figure 10, was composed of two edge-triggered D FFs clocked by the combinational output, with their inputs connected to the principal clock signal. Whenever an invalid change in the combinational signal occurred (i.e., during the active clock cycle), the sensor output was activated. Two FFs were used to detect rising and falling signal transitions. By the addition of independently configurable delay blocks on the combinational output signal and the clock signal, the authors could control the sensor sensitivity (i.e., how late after the rising clock signal a change in the combinational output is detected). When sensitivity is configured to a negative value, the sensor is turned into an early warning monitor, which checks that the signal is stabilized at least by a given time before the clock rises. In comparison with the previously described work, this method bears the great advantage of not requiring extra clock resources for the sensor. On the downside, the approach does not quantitatively measure the propagation delay but rather detects transitions only when slower than a given threshold.

Jiang et al. [54] proposed a similar architecture but connected the inputs Q of both SRs to a shadow clock signal, which had a phase shift relative to the main clock. Given that the frequency of the main clock is known, the authors were able to derive the CUT delay by changing the phase angle between clocks and observing the sensor output.

Discussion. Shadow registers appear more complex to implement and place than ROs, but they provide higher versatility. These sensors enable measuring propagation delays of application-specific circuits (e.g., to characterize chips) as well as implementing late transition detectors. For the detection of transitions within a given time window, this method can verify circuit functionality under different conditions and can even run for continuous monitoring of critical combinational paths to detect degradations caused by BTI and HCI. While ROs either act as probes on unused die areas or temporally replace functioning circuits to test the underlying hardware, SRs are able to run in parallel to application-specific combinational logic. SRs enable at-speed tests, which is a great advantage as they can seamlessly be added concurrently to applications at the cost of additional resource usage.

Propagation delay variations can be detected by observing the Transition Probability (TP) of a circuit [114, 115, 124]. Consider a combinatorial digital circuit with an output node z. For each applied input combination, an output value \(z(k)\) is produced. The transition probability of z, denoted \(D(z)\), is the probability of the state changing when the next input stimuli are applied [38] on the following clock cycle. As z can only be zero or one, \(D(z)\) is the probability of z experiencing a transition between these states:where \(p_z^{0 1}\) and \(p_z^{1 0}\) indicate the probability of z undergoing the \(0 \rightarrow 1\), and \(1 \rightarrow 0\) transitions respectively. From [38], this probability can be calculated as the relative number of transitions that occurred in an interval of N clock cycles with \(N \rightarrow \infty\).

As an example, \(p_z^{1 0}\) can be defined as

If the probabilities are approximated by observing the transitions during a large number N of clock cycles, we obtain

Hence, \(D(z)\) can be estimated by the relative amount of rising and falling edges of z over a time interval N.

Ghosh et al. [38] derived a theorem that relates the output value probability with the input value probability on a combinatorial circuit. If the input signals have a probability distribution independent of time (i.e., they form a stationary process), then the output signal z will also have this characteristic. This means for stationary input signals that the TP \(D(z)\) does not change in time.

Wong et al. [124] estimated the maximum functioning frequency of an arbitrary circuit by measuring its output TP. With a careful selection of the input signals, they ensured a constant TP of the output under normal operating frequencies. They performed various measurements at increasing frequencies, up to the point at which changes in the TP could be observed. The change indicated that the maximum frequency was reached, and the circuit started to fail. The proposed setup was implemented on a 65 nm Altera Cyclone III FPGA, as shown in Figure 11. The CUT and registers were clocked from a test clock generator. On each clock cycle, the test vector generator injected input vectors, which propagated through the CUT, generating an output \(z(k)\). In addition, the sample register captured a sample \(y(k)\) from the CUT at a frequency \(f_{clk}\). An asynchronous counter recorded the transitions in \(y(k)\) over N clock periods, later used to estimate \(D(y)\) in the TP analyser circuit. When \(f_{clk}\) is within the operational range and no faults occur on the circuit, then \(y(k) = z(k)\) and the transition probabilities \(D(y) = D(z)\). If \(f_{clk}\) is increased above the CUT propagation time, then y will start to sample values of the previous cycle (i.e., \(y(k) = z(k - 1)\)), thus, changing \(D(y)\).

The method proposed by Wong et al. [124] was later applied in the study of circuit degradation under accelerated stress conditions by Stott et al. [114, 115]. The authors implemented multiple CUTs on a pair of Cyclone III FPGAs, which could be measured using the TP method and allowed to be electrically stressed by an input signal. Environmental stress with an ageing acceleration factor of 180 was applied to the chips by means of elevated temperature and core voltage, which sped up the NBTI process. Additionally, the CUT was subjected to electrical stress by controlling its switching activity through the input signals, which triggered NBTI, TDDB, and HCI degradation mechanisms. Their experiments revealed a circuit speed reduction of up to 15% by the end of the test schedule. This stress condition degraded LUTs stronger than interconnects. Moreover, the method was verified against an RO-based (see Section 4.1) frequency measurement.

Discussion. Measuring changes in the TP of a CUT output allows for detecting its maximum operational frequency. Unlike ROs (Section 4.1), this method measures the propagation delay of the FPGA using existing circuits; thus, the evaluation of the impact of BTI and HCI processes on the application is more direct. On the one hand, this technique has the advantage of being implementable with common resources and only requires a controllable clock signal. On the other hand, it requires injecting precise test vectors, which depend on the CUT and need to be stored or consistently generated. As custom inputs are needed, this technique affects the system operation and can only be implemented during a testing period.

Chip ageing can degrade signal propagation times, which also affects microcontrollers. Many low-end microcontrollers have a dedicated central clock signal and a short execution pipeline. Under such conditions, a violation of the timing windows, in which data is latched, will cause incorrect data to be propagated down the pipe.

Diggins et al. [31] conjectured a timing window violation hypothesis (Figure 12) which explains the relationship between (i) TID degradation, (ii) operating frequency, and (iii) supply voltage. For each voltage, a maximum operating frequency allows for executing software successfully. This frequency decreases as the TID increases [105]. The authors proposed an offline test to measure the impact of TID in the propagation delay of an ATMEGA328P microcontroller, observing violations on timing windows under multiple voltage and frequency conditions while the device was exposed to different values of TID and executing functional tests. Because the operating core frequency controls the length of the timing windows, software tests were executed at different frequencies. For each value of TID, the highest frequency at which the test passed was recorded. The authors reported that by overclocking the microcontroller above its nominal operational frequency, the degradation of the hardware was observable before a failure occurred at the nominal operating point. This observation bears the potential of developing monitoring techniques that activate predictive maintenance or graceful degradation approaches, such as operating at lower frequencies.

Discussion. The timing window violation hypothesis on microcontrollers has so far only been tested on TID-induced degradation. However, we envision the necessity to evaluate other ageing mechanisms that affect signal propagation delays. Although the analysis of timing window violation based on the clock frequency and operating voltage has mostly been tested in laboratories, great potential lies in online non-concurrent tests due to the high clock reconfigurability of many modern microcontrollers [102].

Many MCUs and FPGAs integrate static RAM (SRAM). A common implementation of an SRAM cell is the six-transistor circuit (Figure 13) owing to its relatively low static power usage. Each cell is composed of two cross-coupled inverters (M1, M2 and M3, M4) and two access transistors (M5 and M6). The cell has two stable states that represent either a logical 0 or 1, depending on the voltage at \(\boldsymbol {Q}\). The word selection line grants access to the cell and connects it to the bit line, which transfers data on read-and-write operations.

When a cell is energized, the initial value is not forced by the bit line; instead, it depends on the mismatch between the threshold voltage of the inverter transistors. The skew of an SRAM cell is its tendency towards a value when powered [49]. A non-skewed cell has a small threshold difference, and its initial value is random and depends on noise. These cells are commonly used as sources of entropy for random number generator systems. Cells with a moderate mismatch have a tendency towards a particular value, but this can be affected by ageing mechanisms that influence the threshold voltage of transistors, such as BTI. Finally, fully skewed cells produce the same initial value with a high probability and can be used to implement SRAM physically unclonable functions.

The Static Noise Margin (SNM) of an SRAM cell is the lowest level of voltage noise that flips its logic state. As the SNM depends on the transistor threshold voltage, ageing degrades it. Degraded SNM makes cells more sensitive to electric and thermal noise. A degradation of 15.02% of the SNM has been reported [33] after 10 years of usage owing to BTI effects. The skew of a cell is also impacted by BTI and HCI. Considering a cell that is constantly stressed by retaining a logical 1 on its output, the P-MOS M2 transistor in Figure 13 is active and undergoes a degradation process that modifies its threshold voltage during this time. If, upon startup, the gate threshold voltage of M2 is much larger than that of M4, the cell will be skewed towards 0 because M4 will be activated before M2.

The skew change of SRAM cells over time has been exploited by Guo et al. [47] as a two-phase method to detect recycled SoCs and FPGA chips. This was later refined as a framework [48]. Authors proposed an initial enrolment phase to detect partially skewed cells, which would likely change their startup value when aged. The authors first calculated the probability of starting in 0 and 1 for all SRAM bits, respectively, assuming room and high temperature for a given number of startup cycles. The underlying method foresees that high ambient temperature produces a good prediction for the aged state of the bits. By calculating the difference between the probabilities and comparing it to a pre-selected gap value, they selected the “ageing-sensitive” bits. A chosen threshold value determined the number of flipped bits required to consider a device as used (i.e., aged) during the verification phase. The gap value used to select the ageing-sensitive bits is not universal, and the authors indicated that it should be determined empirically based on measurements of aged devices beforehand. Tests on artificially aged Xilinx Spartan-3 FPGAs showed false accept and reject rates of 0 and 0.03, respectively, when picking the proper parameters.

Guin et al. [44] also proposed a method to detect recycled SoCs and FPGAs based on the assumption that SRAM cells are balanced by design. The authors argued that any bias introduced during manufacturing is random and that the amount of 1s and 0s normally distributes with a centre very close to 50% (i.e., within 1%). Therefore, any significant shift of the mean would be the result of circuit ageing. The technique requires no initial measurement phase or a golden model against which to compare. The approach only requires that the circuit is powered up multiple times to count the amount of 1s. The authors suggested that having a large enough SRAM array (e.g., 64 kbit) and taking sufficient measurements (e.g., 100) would minimize the impact of thermal noise during the assessment. Tests on COTS external SRAM chips showed significant changes in the distribution (up to 14% after ageing) and a slight recovery when stress was removed.

Lanzieri et al. [70] collected and studied SRAM startup patterns from MCUs of 154 naturally aged embedded devices deployed on an IoT testbed. The authors analysed the raw patterns and extracted subtle features, including spatial frequency components, bitwise probability of ones, and bit instability, to unveil correlations with the effective usage times of the devices. The observation of the extracted features revealed not only linear correlations with the usage time, but also discernible patterns in how the firmware interacts with the SRAM, such as initializing variables to 0 and determining their placement within the memory map. Finally, the authors trained and compared ML regression and classification models with the result of the feature engineering process, successfully evaluating the application of the SRAM startup pattern as a ubiquitous and inexpensive on-chip usage monitor.

Discussion. Given the ubiquity of SRAMs in various digital integrated circuits, the use of its initial pattern for indicating transistor degradation is an interesting and deployable method that requires no external equipment. The present work shows that BTI effects are already detectable on SRAMs after a few hours of accelerated ageing as well as in long-term naturally aged deployments. To take further advantage of modifications in SRAM startup patterns and to integrate them into higher-level health assessment systems, it is required to research correlations between the observed changes and the degradation of functional parameters of interest, such as the SNM.

Electronic device ageing affects EM characteristics, such as conducted and radiated emissions [15] as well as susceptibility [74]. By subjecting devices to EM Compatibility (EMC) tests, their effective ageing could be determined.

Dawson et al. [30] proposed a method to study the effect of high temperature ageing on the EM emissions of a COTS MCU. The authors proposed to monitor device emissions as a reliable and straightforward measure to monitor ageing, as no electrical contact with the system is required. An emission test board was built containing a Microchip PIC MCU with pins connected to loaded tracks passing by RF couplers. During tests, the software running on the device toggled the pins while a spectrum analyser captured EM emissions and the output voltage was measured at the pins. The authors reported variations in the emission spectra of artificially aged devices. Some harmonics of the central toggling frequency increased, particularly the high-frequency harmonics. It remains unclear whether a shift in the toggling frequency is the culprit. Additionally, the output voltage on aged devices increased, but there were no conclusions regarding the reasons for the reported behaviour. Although no clear mechanism linking the changes in emissions to device ageing was presented, BTI is a likely candidate due to the temperature-triggered nature of the changes.

EM Robustness (EMR) studies the impact of circuit ageing on EMC [11]. Li, Wu et al. [74, 126] analysed the drift in the EM immunity of an MCU to Electrical Fast Transients (EFTs) interference after accelerated ageing. They aged the device in incremental steps by applying high voltage (150% above nominal) and high temperature. The test setup consisted of a probe connecting the device to an EFT signal generator, which injected an interference signal between each ageing step. To assess whether the device was affected by the signal, errors were monitored for the executed software. The authors reported failures, including self-recovering errors, soft errors (reset was needed) and complete damage. Failure rates increased consistently with the ageing time, as well as immunity degradation (observed as a decrement in the maximum tolerated interference voltage for some pins). No further analysis was performed relating internal ageing mechanisms under the observed results. Instead, authors suspected that (i) physical parameters of the functional components of the MCU drifted due to ageing, and (ii) components of the EM interference protection circuitry degraded, thus increasing susceptibility.

Discussion. Although related work reveals a clear impact of circuit degradation in the EMC and EMR of MCUs, the inner dynamics of this phenomenon are still to be explored. As MCUs are complex devices, it is challenging to assess the degradation of every subsystem and their impact on the EM spectrum signature. EM measurements have not been widely developed as ageing monitoring techniques. This may be due to requiring external equipment and limited understanding of the correlation between system degradation of circuits and the changes in EM characteristics. This gap opens an interesting research direction for studying correlations between other ageing indicators for MCUs and SOCs (e.g., SRAM startup patterns) and EMC, which could enable indirect measurements of the latter by means of cheaper and ubiquitous sensors that require no external equipment.

The Power Supply Rejection Ratio (PSRR) is an important characteristic of LDO regulators. It indicates its ability to prevent fluctuations in the output voltage in the presence of noise from the input voltage (or power supply voltage). The PSRR is the relation between the output voltage ripple \(v_o\) and the input voltage ripple \(v_i\). It is normally measured for the whole operating frequency band of the regulator. A typical PSRR characteristic is illustrated in Figure 16; a lower value means a better rejection of the power supply noise. The PSRR in the frequency domain can be modelled as in Equation (10) [27]. The constant K depends on the feedback resistors, the load, and the internal drain-to-source resistance to the small signal of the transistor. The frequencies \(\omega _a\) and \(\omega _o\) are poles of the PSRR transference equation and depend on the resistances and capacitances of the transistor, the amplifier, and the load circuit. \(A_a\) and \(A_o\) are the loop gains of the amplifier and pass transistor, respectively.

with the feedback loop transfer function,

The PSSR curve (Figure 16) has two regions: Region 1 at low and middle frequencies and Region 2 at high frequencies. Both regions meet at the unity bandwidth frequency \(\omega _{REG}\), where the feedback loop gain is one. Region 1 is governed by the loop gain, which depends on the transconductance of the pass transistor and the amplifier. As this property is affected by transistor ageing mechanisms (e.g., BTI and HCI), the PSRR is impacted by circuit ageing. Region 2 is mainly impacted by parasitic capacitances of the transistor input and the load, whereas the feedback loop gain plays almost no role. HCI changes the gate capacitance of transistors [51], thus also modifying the PSRR in this region.

Considering the effect of circuit ageing on the PSRR, Chowdhury et al. [28] proposed using this parameter to estimate the ageing of LDOs as well as ICs, including such components in their power delivery networks, with the goal of determining whether a device has been recycled. To characterize the impact of ageing in the PSRR, the authors designed their own LDO chips in 65 nm technology. The LDOs were artificially aged at elevated temperature and power supply voltage. To analyse the PSRR of the devices and to record the output spectrum, a spectrum analyser and its tracking generator were employed. After applying AC and DC stress to the LDO, a degradation of the PSRR was observed as well as a shift in the transfer poles. This shows that both NBTI (DC stress) and HCI (AC stress) mechanisms could be detected by measuring the PSRR degradation.

Based on the clear influence of circuit ageing on the PSRR [28], the authors introduced a technique [26, 27] based on ML methods that utilizes this parameter to detect recycled analog and mixed-signal chips and SoCs, respectively. As a first step, an unsupervised k-Nearest Neighbours (KNN) model was trained and tested with PSRR data from new and artificially aged devices from one vendor. Next, the authors used a semi-supervised approach, in which they applied the previously trained models and tested them against other vendors in an attempt to avoid the need of golden data from all vendors. Both approaches showed promising results in discriminating used and new LDOs but required golden data and a supervised training phase. Finally, for unsupervised learning, two cases were tested. (i) PSRR data from an unknown device was given to the model together with golden data and, based on the number of clusters returned, the device could be classified as new or aged. (ii) The PSRRs of the unknown device were measured twice, before and after a synthetic ageing process. This last approach had the clear downside of being partially destructive and did not show good results.

Acharya et al. [2] presented and implemented an odometer based on a modified LDO circuit intended for the ageing-based detection of recycled ICs. A parallel feedback path to the regulator (i.e., a reference path) was added, which remained unused throughout the device lifetime. Two signals controlled which path is actively used. A one-label classifier model evaluated the LDO PSRR when using each path to detect degradation in the regulator components. Besides the external measurements, this method has the drawbacks of requiring a custom regulator design (i.e., cannot be applied on COTS components) and employing redundant hardware.

Discussion. Measuring PSRR changes has proven effective for detecting ageing of external LDO regulators. Although Chowdhury et al. [26, 28] claim that the proposed methods are applicable to ICs, they were only tested on stand-alone LDOs. Measurements of embedded LDOs were solely presented in [27], but the applied models could not detect recycled chips. In addition, the reported results are based on artificially aged devices due to the lack of used chips. Given its direct relation to transistor parameters, PSRR is a sensible parameter to reveal ageing effects of BTI and HCI on LDOs. Thus far, the literature has only focused on short ageing periods, however; a few hours under accelerated ageing correspond to a few days of normal operation. To fully understand the correlation of PSRR with device ageing over longer periods of time, further research is required. Moreover, methods proposed so far heavily rely on external testing equipment, and no strategy has yet been presented to deploy testing in the field.

Ageing not only affects the EM characteristics of microcontrollers and SoCs (see Section 5.3) but also those of LDOs [127] and SMPSs [17]. Indeed, as parameters of the voltage regulator shift away from their nominal values due to degradation, so do their EM emissions and susceptibility.

Boyer et al. [17] have studied how thermally triggered ageing mechanisms affect internal passive and switching components of SMPS in step-down or buck configuration, thus modifying its conducted and radiated EM emissions. To this end, they have artificially aged four samples of NCP3163 devices at elevated temperature. Although all samples remained operational after ageing, an average increase between 6 dB and 20 dB in the conducted emissions and 5 dB in the radiated emissions spectra were observed over a large frequency range. The aged inductor was replaced by a new component to determine its impact on the system degradation, which lowered EM emissions according to their initial values. By means of an impedance versus frequency characterization of the inductor before and after thermal stress, the authors encountered a reduction in its impedance and quality factor, which was attributed to an increase in the parasitic parallel capacitor caused by a higher core loss as described in Section 2.3.2.

Boyer et al. [16] also performed related experiments on synchronous buck converters based on the LT3800 controller. Measurements of conducted EM emissions were carried out inside a semi-anechoic chamber. Converter boards and various additional components were aged in an oven at high temperature for 2 weeks. The power iron inductor and aluminium capacitor were the most degraded components, followed by the onboard output capacitor and the power transistors. In addition, the conducted emission measured at the circuit output suffered an increment of up to 15 dB between 4 MHz and 100 MHz.

As analysed in detail by Wu et al. [127], EMI-induced offset is a common failure mode caused by EM noise coupled to the power pin of an LDO. Due to the nonlinearity of the differential transistor pair at the input of the comparator amplifier (see Figure 15), noise injected via the power network induces an offset of the output voltage via a rectification effect. A test bench was built with a signal generator coupled to the voltage source and an oscilloscope monitoring the output and reference voltage. Various devices were aged for a week by electrically stressing them to evaluate the relation between ageing mechanisms and EM susceptibility. The devices still functioned, but their EMI robustness decreased. This indicated that the stress process had indeed triggered the transistor ageing mechanisms in the operational amplifier of the LDO.

Discussion. Component degradation alters EM emissions and affects susceptibility of power supplies. The main culprits are ageing on passive components (via ESR changes on capacitors or quality factor reduction on inductors) and switching components (mainly due to BTI and HCI). Although EM characteristics are indicators of these ageing effects, measurements can be troublesome. EM-based ageing detection methods developed in the literature typically require special setups, procedures, and external equipment, which hinders deployment as an online monitoring technique. Moreover, the usage of expensive dedicated instruments contradicts many typical requirements for COTS-based embedded applications, namely, low cost, low power usage, and small size.

Capacitors are widely used as low-pass filters to clean noise from power lines (e.g., to suppress the switching noise introduced by SMPS as visualized Figure 14). Capacitor degradation jeopardizes the availability of the circuit. In fact, electrolytic capacitor failures cause more than 50% of SMPS breakdowns [68]. As digital components require a stable voltage, capacitors are attractive for degradation studies.

The impact of ageing mechanisms on the output voltage ripple of SMPS has been studied in [17]. Several DC-DC switching step-down circuits were subjected to accelerated ageing via increased temperature. The authors reported an increase between 100% and 200% in the output noise after ageing. It was determined that the main culprits for the decay in voltage stability were the filtering electrolytic capacitors at the output. Indeed, the high temperature accelerated the ageing mechanism described in Section 2.3.1. As a consequence, the equivalent serial resistance increased and the capacitance decayed.

As the ESR usually changes more than the capacitance for a given ageing, the former is preferred for monitoring purposes. To prevent failures, it is usually a good practice to replace a component whose ESR has increased by 100% or more [36].

Givi et al. [39] proposed and implemented an online concurrent monitoring system for DC-DC converters. Their technique detects ageing at the power supply output capacitor by indirectly measuring its ESR. The proposed setup required two voltage sensors at the converter: a Rogowski coil sensor on the inductor and a sensor of the output voltage. The authors implemented a monitoring system that derived the capacitor ESR on software from measurements of these two voltages using a DS1104 controller board. By comparing the resistance value with the initial one, the degradation of the component was estimated, and a warning signal could be triggered.

Lahyani et al. [68] argued that only the waveform of the output voltage ripple changes when capacitors degrade. They developed a software-based ESR monitoring method that sampled this ripple and applied a band-pass filter to the signal. They found that measuring the ripple at the power supply switching frequency is a more realistic method than using an average rectified value, and it reduces the load dependence.

On the other hand, Chen et al. [23] also measured ESR by observing the output voltage but proposed to filter out the switching frequency. Following a theoretical analysis, the authors concluded that the amplitude of the output voltage ripple could be accurately modelled as a direct, linear dependence on the ESR. Additionally, they showed that the output voltage ripple barely varies when the load current changes because the capacitor is part of an LC filter. From this, authors derived a method for failure prediction, which measured and processed the capacitor voltage, as illustrated in Figure 17. A band-pass filter eliminates the DC component and the power supply switching frequency from the signal. After injecting the signal into a rectifier and a low-pass filter, a voltage proportional to the capacitor ESR can be obtained. When compared with a predefined threshold voltage, an early warning trigger signal can be generated. An additional delay circuit serves as mitigation against fake measurements during the circuit startup transient.

Discussion. The literature agrees that the output capacitor ESR serves as a good indicator to assess the overall health of a power supply, mainly due to the high impact of this component in the correct operation of the system. Additionally, its measurement is relatively simple. Given the ubiquity of analog-to-digital converters on most modern microcontrollers of embedded applications, it would be of interest to build in a concurrent online test that performed the signal processing completely digitally without extra circuitry. On the other hand, a drawback of this approach is the high susceptibility of ESR to operating conditions. Although it has been shown [23, 39, 68] that changes in the load do not affect the measurement, ESR still changes significantly with temperature and frequency. Systems also need to measure the environment and keep a record of the initial value under different conditions to account for these changes.