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A VLIW architecture for a trace scheduling compiler

Authors:

Robert P. Colwell,

John J. O'Donnell,

David B. Papworth,

Paul K. RodmanAuthors Info & Claims

ASPLOS II: Proceedings of the second international conference on Architectual support for programming languages and operating systems

Pages 180 - 192

https://doi.org/10.1145/36206.36201

Published: 01 October 1987 Publication History

Abstract

Very Long Instruction Word (VLIW) architectures were promised to deliver far more than the factor of two or three that current architectures achieve from overlapped execution. Using a new type of compiler which compacts ordinary sequential code into long instruction words, a VLIW machine was expected to provide from ten to thirty times the performance of a more conventional machine built of the same implementation technology.Multiflow Computer, Inc., has now built a VLIW called the TRACE^TM along with its companion Trace Scheduling^TM compacting compiler. This new machine has fulfilled the performance promises that were made. Using many fast functional units in parallel, this machine extends some of the basic Reduced-Instruction-Set precepts: the architecture is load/store, the microarchitecture is exposed to the compiler, there is no microcode, and there is almost no hardware devoted to synchronization, arbitration, or interlocking of any kind (the compiler has sole responsibility for runtime resource usage).This paper discusses the design of this machine and presents some initial performance results.

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Cited By

Jacob B(2016)The Case for VLIW-CMP as a Building Block for ExascaleIEEE Computer Architecture Letters10.1109/LCA.2015.242469915:1(54-57)Online publication date: 1-Jan-2016
https://dl.acm.org/doi/10.1109/LCA.2015.2424699
McFarlin DZilles C(2015)Branch vanguardACM SIGARCH Computer Architecture News10.1145/2872887.275040043:3S(323-335)Online publication date: 13-Jun-2015
https://dl.acm.org/doi/10.1145/2872887.2750400
McFarlin DZilles CMarr DAlbonesi D(2015)Branch vanguardProceedings of the 42nd Annual International Symposium on Computer Architecture10.1145/2749469.2750400(323-335)Online publication date: 13-Jun-2015
https://dl.acm.org/doi/10.1145/2749469.2750400
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A VLIW architecture for a trace scheduling compiler

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A VLIW architecture for a trace scheduling compiler

Very Long Instruction Word (VLIW) architectures were promised to deliver far more than the factor of two or three that current architectures achieve from overlapped execution. Using a new type of compiler which compacts ordinary sequential code into ...
A VLIW architecture for a trace scheduling compiler

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A VLIW architecture for a trace Scheduling Compiler
Special issue on architectural support for programming languages and operating systems

A VLIW (very long instruction word) architecture machine called the TRACE has been built along with its companion Trace Scheduling compacting compiler. This machine has three hardware configurations, capable of executing 7, 14, or 28 operations ...

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Published In

cover image ACM Conferences

ASPLOS II: Proceedings of the second international conference on Architectual support for programming languages and operating systems

October 1987

205 pages

ISBN:0818608056

DOI:10.1145/36206

Editor:
Randy Katz
Univ. of California, Berkeley
,
General Chair:
Martin Freeman
Stanford University and Philips/Signetics

ACM SIGPLAN Notices Volume 22, Issue 10
Oct. 1987
189 pages
ISSN:0362-1340
EISSN:1558-1160
DOI:10.1145/36205
Editor:
Randy Katz
Univ. of California, Berkeley
Issue’s Table of Contents
ACM SIGOPS Operating Systems Review Volume 21, Issue 4
Oct. 1987
189 pages
ISSN:0163-5980
DOI:10.1145/36204
Editor:
Randy Katz
Univ. of California, Berkeley
Issue’s Table of Contents
ACM SIGARCH Computer Architecture News Volume 15, Issue 5
Oct. 1987
189 pages
ISSN:0163-5964
DOI:10.1145/36177
Editor:
Randy H. Katz
Univ. of California, Berkeley
Issue’s Table of Contents

Copyright © 1987 Copyright is held by the owner/author(s).

Permission to make digital or hard copies of part or all of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for third-party components of this work must be honored. For all other uses, contact the Owner/Author.

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Association for Computing Machinery

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Published: 01 October 1987

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ASPLOS II: Architectual support for programming languages and operating systems

October 5 - 8, 1987

California, Palo Alto, USA

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Cited By

Jacob B(2016)The Case for VLIW-CMP as a Building Block for ExascaleIEEE Computer Architecture Letters10.1109/LCA.2015.242469915:1(54-57)Online publication date: 1-Jan-2016
https://dl.acm.org/doi/10.1109/LCA.2015.2424699
McFarlin DZilles C(2015)Branch vanguardACM SIGARCH Computer Architecture News10.1145/2872887.275040043:3S(323-335)Online publication date: 13-Jun-2015
https://dl.acm.org/doi/10.1145/2872887.2750400
McFarlin DZilles CMarr DAlbonesi D(2015)Branch vanguardProceedings of the 42nd Annual International Symposium on Computer Architecture10.1145/2749469.2750400(323-335)Online publication date: 13-Jun-2015
https://dl.acm.org/doi/10.1145/2749469.2750400
Thon LRimey KSvensson L(2011)From C to SiliconAnatomy of a Silicon Compiler10.1007/978-1-4615-3570-6_17(251-268)Online publication date: 31-Mar-2011
https://doi.org/10.1007/978-1-4615-3570-6_17
Ramachandran AJacome M(2010)Power-Aware Embedded ComputingEmbedded Systems Handbook, Second Edition10.1201/9781439807637.ch11(11-1-11-25)Online publication date: 30-Apr-2010
https://doi.org/10.1201/9781439807637.ch11
Verma SBiswas RSingh J(2010)Extension of Superblock Technique to Hyperblock Using Predicate Hierarchy GraphContemporary Computing10.1007/978-3-642-14825-5_19(217-229)Online publication date: 2010
https://doi.org/10.1007/978-3-642-14825-5_19
Gupta MSanchez F(2007)Cluster-level simultaneous multithreading for VLIW processors2007 25th International Conference on Computer Design10.1109/ICCD.2007.4601890(121-128)Online publication date: Oct-2007
https://doi.org/10.1109/ICCD.2007.4601890
Gupta MSanchez FLlosa J(2007)Merge Logic for Clustered Multithreaded VLIW Processors10th Euromicro Conference on Digital System Design Architectures, Methods and Tools (DSD 2007)10.1109/DSD.2007.4341492(353-360)Online publication date: Aug-2007
https://doi.org/10.1109/DSD.2007.4341492
Lam M(2004)Software pipeliningACM SIGPLAN Notices10.1145/989393.98942039:4(244-256)Online publication date: 1-Apr-2004
https://dl.acm.org/doi/10.1145/989393.989420
Chen SFuchs W(2001)Compiler-Assisted Multiple Instruction Word Retry for VLIW ArchitecturesIEEE Transactions on Parallel and Distributed Systems10.1109/71.97056412:12(1293-1304)Online publication date: 1-Dec-2001
https://dl.acm.org/doi/10.1109/71.970564
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