research-article

Compiler-Assisted Multiple Instruction Word Retry for VLIW Architectures

Authors:

Shyh-Kwei Chen,

W. Kent FuchsAuthors Info & Claims

IEEE Transactions on Parallel and Distributed Systems, Volume 12, Issue 12

Pages 1293 - 1304

https://doi.org/10.1109/71.970564

Published: 01 December 2001 Publication History

Abstract

Very Long Instruction Word (VLIW) architectures can enhance performance by exploiting fine-grained instruction level parallelism. In this paper, we describe a compiler assisted multiple instruction word retry scheme for VLIW architectures. A read buffer is used to resolve the more frequent on-path hazards, while the compiler resolves the remaining branch hazards. Performance evaluation is described for 11 benchmark programs based on the IBM VLIW research compiler, Chameleon. Experimental results indicate that, for a VLIW machine with P functional units to rollback N instruction words, a read buffer of 2NP entries with the compiler assist can be an effective approach in producing low overhead runtime performance and small code growth, for P = 4, 8, 12, and 16 and N \leq 3.

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Cited By

Jiang J(2018)An error recoverable structure based on complementary logic and alternating-retryJournal of Computer Science and Technology10.1007/s11390-005-0885-420:6(885-894)Online publication date: 21-Dec-2018
https://dl.acm.org/doi/10.1007/s11390-005-0885-4
Bonnoit TNicolaidis MZergainoh N(2018)Using Error Correcting Codes Without Speed Penalty in Embedded MemoriesJournal of Electronic Testing: Theory and Applications10.1007/s10836-013-5386-829:3(383-400)Online publication date: 28-Dec-2018
https://dl.acm.org/doi/10.1007/s10836-013-5386-8

Index Terms

Compiler-Assisted Multiple Instruction Word Retry for VLIW Architectures
1. Computer systems organization
  1. Architectures
    1. Parallel architectures
      1. Multiple instruction, multiple data
  2. Dependable and fault-tolerant systems and networks
2. Software and its engineering
  1. Software notations and tools
    1. Compilers

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cover image IEEE Transactions on Parallel and Distributed Systems

IEEE Transactions on Parallel and Distributed Systems Volume 12, Issue 12

December 2001

148 pages

ISSN:1045-9219

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Copyright © Copyright © 2001 IEEE. All Rights Reserved.

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IEEE Press

Publication History

Published: 01 December 2001

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Cited By

Jiang J(2018)An error recoverable structure based on complementary logic and alternating-retryJournal of Computer Science and Technology10.1007/s11390-005-0885-420:6(885-894)Online publication date: 21-Dec-2018
https://dl.acm.org/doi/10.1007/s11390-005-0885-4
Bonnoit TNicolaidis MZergainoh N(2018)Using Error Correcting Codes Without Speed Penalty in Embedded MemoriesJournal of Electronic Testing: Theory and Applications10.1007/s10836-013-5386-829:3(383-400)Online publication date: 28-Dec-2018
https://dl.acm.org/doi/10.1007/s10836-013-5386-8

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