Nothing Special   »   [go: up one dir, main page]

skip to main content
article
Free access

Modeling layout tools to derive forward estimates of area and delay at the RTL level

Published: 01 July 2000 Publication History

Abstract

Forward estimates of area and delay facilitate effective decision-making when searching the solution space of digital designs. Current estimation techniques focus on modeling the layout result and fail to deliver timely or accurate estimates. This paper presents a novel approach to deriving these area and delay estimates at the RTL level by modeling the layout tool, rather than the layout result. This approach uses machine learning techniques to capture the relationships between general design features (i.e., topology, connectivity, common input, and common output) and layout concepts (i.e., relative placement). Experiments illustrate the formulation of the training set for machine learning in this domain, and also show how we can derive different tool models. Finally, they show how we can use the resultant model to derive forward estimates of area and delay in real-world designs.

References

[1]
BREUER, M. 1977. Min-cut placement. J. Des. Autom. Fault-Tolerant Comput., 343-362.
[2]
BUCHANAN, B. AND SHORTLIFFE, E. 1984. Rule-Based Expert Systems. Addison-Wesley, Reading, MA.
[3]
HAKIMI, S. 1971. Steiner's problem in graphs and its implications. Networks 1, 113-133.
[4]
HSIEH, Y. -W. 1992. Architectural synthesis via VHDL. Master's Thesis. University of Pittsburgh, Pittsburgh, PA.
[5]
IRWIN, M. g. AND OWENS, R. M. 1989. A comparison of four two-dimensional gate matrix layout tools. In Proceedings of the 26th ACM/IEEE Conference on Design Automation (DAC '89, Las Vegas, NV, June 25-29, 1989), D. E. Thomas, Ed. ACM Press, New York, NY, 698-701.
[6]
JAIN, R., PARKER, A. C., AND PARK, N. 1992. Predicting system-level area and delay for pipelined and non-pipelined designs. IEEE Trans. Comput.-Aided Des. 12, 8 (Aug.).
[7]
KANG, S. 1983. Linear ordering and application to placement. In Proceedings of the 20th ANSI/IEEE Conference on Design Automation (Miami Beach, FL, June 27 - 29), IEEE Computer Society Press, Los Alamitos, CA, 457-464.
[8]
KIM, S. 1992. CMOS VLSI layout synthesis for circuit performance. Ph.D. Dissertation. Pennsylvania State University, University Park, PA.
[9]
KNAPP, D.W. 1992. FASOLT: A program for feedback-driven data-path optimization. IEEE Trans. Comput.-Aided Des. 11, 6 (June), 677-695.
[10]
KURDAHI, F. J. AND PARKER, A. C. 1989. Techniques for area estimation of VLSI layouts. IEEE Trans. Comput.-Aided Des. 8, 1 (Jan.), 81-92.
[11]
LANDMAN, B. AND RUSSO, R. 1971. On a pin versus block relationship for partition of logic graphs. IEEE Trans. Comput. C-20 (Apr.).
[12]
LAUTHER, U. 1988. A min-cut placement algorithm for general cell assemblies based on a graph representation. In A Compendium of Papers from the Design Automation Conference on Twenty-Five Years of Electronic Design Automation (DAC '88), A. R. Newton, Ed. ACM Press, New York, NY, 182-191.
[13]
MANBER, U. 1989. Introduction to Algorithms. Addison-Wesley, Reading, MA.
[14]
NOURANI, M. AND PAPACHRISTOU, C. 1993. A layout estimation algorithm for RTL datapaths. In Proceedings of the 30th ACM/IEEE International Conference on Design Automation (DAC '93, Dallas, TX, June 14-18), A. E. Dunlop, Ed. ACM Press, New York, NY, 285-291.
[15]
PROVOST, J. F. 1992. Policies for the selection of bias in inductive machine learning. Ph.D. Dissertation. University of Pittsburgh, Pittsburgh, PA.
[16]
RAMACHANDRAN, C. AND KURDAHI, F.g. 1992a. TELE: A timing evaluator using layout estimation for high level applications. In Proceedings of the European Conference on Design Automation (EDAC '92, Brussels, Belgium, Mar. 16 - 19), IEEE Computer Society Press, Los Alamitos, CA, 137-141.
[17]
RAMACHANDRAN, C. AND KURDAHI, F.J. 1992b. Combined topological and functionality based delay estimation using a layout-driven approach for high level applications. In Proceedings of the European Conference on Design Automation (EURO-DAC '92, Hamburg, Germany, Sept. 7-10, 1992), G. Musgrave, Ed. IEEE Computer Society Press, Los Alamitos, CA, 72-78.
[18]
RAMACHANDRAN, C., KURDAHI, F. J., GAJSKI, D. D., Wu, A. C.-H., AND CHAIYAKUL, V. 1992. Accurate layout area and delay modeling for system level design. In Proceedings of the 1992 IEEE/ACM International Conference on Computer-Aided Design (ICCAD '92, Santa Clara, CA, Nov. 8-12), L. Trevillyan, Ed. IEEE Computer Society Press, Los Alamitos, CA, 355-361.
[19]
RUTENBAR, R.A. 1989. Simulated annealing algorithms: An overview. IEEE Circ. Dev. 5, 1 (Jan.), 19-26.
[20]
TERMAN, C. 1983. Simulation tools for digital LSI design. Ph.D. Dissertation. MIT Laboratory for Computer Science, Cambridge, MA.
[21]
WEISS, S. M. AND KULIKOWSKI, C.A. 1991. Computer Systems That Learn: Classification and Prediction Methods from Statistics, Neural Nets, Machine Learning, and Expert Systems. Morgan Kaufmann Publishers Inc., San Francisco, CA.

Recommendations

Comments

Please enable JavaScript to view thecomments powered by Disqus.

Information & Contributors

Information

Published In

cover image ACM Transactions on Design Automation of Electronic Systems
ACM Transactions on Design Automation of Electronic Systems  Volume 5, Issue 3
July 2000
483 pages
ISSN:1084-4309
EISSN:1557-7309
DOI:10.1145/348019
Issue’s Table of Contents
Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

Publisher

Association for Computing Machinery

New York, NY, United States

Journal Family

Publication History

Published: 01 July 2000
Published in TODAES Volume 5, Issue 3

Permissions

Request permissions for this article.

Check for updates

Author Tags

  1. VLSI CAD
  2. estimation
  3. estimation techniques
  4. layout
  5. machine learning

Qualifiers

  • Article

Contributors

Other Metrics

Bibliometrics & Citations

Bibliometrics

Article Metrics

  • 0
    Total Citations
  • 512
    Total Downloads
  • Downloads (Last 12 months)52
  • Downloads (Last 6 weeks)9
Reflects downloads up to 12 Nov 2024

Other Metrics

Citations

View Options

View options

PDF

View or Download as a PDF file.

PDF

eReader

View online with eReader.

eReader

Get Access

Login options

Full Access

Media

Figures

Other

Tables

Share

Share

Share this Publication link

Share on social media