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Software-like Compilation for Data Center FPGA Accelerators

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HEART '21: Proceedings of the 11th International Symposium on Highly Efficient Accelerators and Reconfigurable Technologies

Article No.: 3, Pages 1 - 6

https://doi.org/10.1145/3468044.3468047

Published: 21 June 2021 Publication History

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Abstract

Compilation times for large Xilinx devices, such as the Amazon F1 instance, are on the order of several hours. However, today's data center designs often have many identical processing units (PUs), meaning that conventional design flows waste time placing and routing the same problem many times. Furthermore, the connectivity infrastructure of a design tends to be finalized before the PUs, resulting in unnecessary recompilation of a large fraction of the design.

We present an open source flow where the connectivity infrastructure logic is implemented ahead of time and routed to many interface blocks that border available slots for PUs. As architects iterate on their PU designs, they only need to perform a single set of parallel, independent compile runs to implement and route the PU alongside each distinct interface block. Our RapidWright-based system stitches the implemented PU into the available slots in the connectivity logic, requiring no additional routing to finalize the design. Our system is able to generate working designs for Amazon F1, and reduces compilation time over the standard monolithic compilation flow by an order of magnitude for designs with up to 180 PUs. Our experiments also show that there is future potential for an additional 4X runtime improvement when relying on emerging open source place and route tools.

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Cited By

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Xiao YPark DNiu ZHota ADehon A(2024)ExHiPR: Extended High-Level Partial Reconfiguration for Fast Incremental FPGA CompilationACM Transactions on Reconfigurable Technology and Systems10.1145/361783717:2(1-28)Online publication date: 13-Mar-2024
https://dl.acm.org/doi/10.1145/3617837
Park DXiao YDeHon A(2022)Fast and Flexible FPGA Development using Hierarchical Partial Reconfiguration2022 International Conference on Field-Programmable Technology (ICFPT)10.1109/ICFPT56656.2022.9974201(1-10)Online publication date: 5-Dec-2022
https://doi.org/10.1109/ICFPT56656.2022.9974201
Xiao YHota APark DDeHon A(2022)HiPR: High-level Partial Reconfiguration for Fast Incremental FPGA Compilation2022 32nd International Conference on Field-Programmable Logic and Applications (FPL)10.1109/FPL57034.2022.00022(70-78)Online publication date: Aug-2022
https://doi.org/10.1109/FPL57034.2022.00022
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Published In

HEART '21: Proceedings of the 11th International Symposium on Highly Efficient Accelerators and Reconfigurable Technologies

June 2021

76 pages

ISBN:9781450385497

DOI:10.1145/3468044

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than the author(s) must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected].

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German Research Foundation: German Research Foundation

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Association for Computing Machinery

New York, NY, United States

Publication History

Published: 21 June 2021

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HEART '21

HEART '21: International Symposium on Highly Efficient Accelerators and Reconfigurable Technologies

June 21 - 23, 2021

Online, Germany

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Overall Acceptance Rate 22 of 50 submissions, 44%

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Cited By

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Xiao YPark DNiu ZHota ADehon A(2024)ExHiPR: Extended High-Level Partial Reconfiguration for Fast Incremental FPGA CompilationACM Transactions on Reconfigurable Technology and Systems10.1145/361783717:2(1-28)Online publication date: 13-Mar-2024
https://dl.acm.org/doi/10.1145/3617837
Park DXiao YDeHon A(2022)Fast and Flexible FPGA Development using Hierarchical Partial Reconfiguration2022 International Conference on Field-Programmable Technology (ICFPT)10.1109/ICFPT56656.2022.9974201(1-10)Online publication date: 5-Dec-2022
https://doi.org/10.1109/ICFPT56656.2022.9974201
Xiao YHota APark DDeHon A(2022)HiPR: High-level Partial Reconfiguration for Fast Incremental FPGA Compilation2022 32nd International Conference on Field-Programmable Logic and Applications (FPL)10.1109/FPL57034.2022.00022(70-78)Online publication date: Aug-2022
https://doi.org/10.1109/FPL57034.2022.00022
Zhou YMaidee PLavin CKaviani AStroobandt D(2021)RWRoute: An Open-source Timing-driven Router for Commercial FPGAsACM Transactions on Reconfigurable Technology and Systems10.1145/349123615:1(1-27)Online publication date: 29-Nov-2021
https://dl.acm.org/doi/10.1145/3491236

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