Article

Using Relocatable Bitstreams for Fault Tolerance

Authors:

David P. Montminy,

Rusty O. Baldwin,

Paul D. Williams,

Barry E. MullinsAuthors Info & Claims

AHS '07: Proceedings of the Second NASA/ESA Conference on Adaptive Hardware and Systems

Pages 701 - 708

https://doi.org/10.1109/AHS.2007.108

Published: 05 August 2007 Publication History

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Abstract

The regular structure and addressing scheme for the Virtex-II family of Field Programmable Gate Arrays (FPGAs) allows the relocation of partial bitstreams through direct bitstream manipulation. Our bitstream translation program relocates modules on an FPGA by changing the partial bitstream of the module. To take advantage of relocatable modules, three fault tolerant circuit designs are developed and tested. While operating through a fault, these designs provide support for efficient and transparent replacement of the faulty module with a relocated fault-free module. The architecture of the FPGA and static logic significantly constrain the placement of relocatable modules, especially when a microprocessor is placed on the FPGA.

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Thomas JLavin CKaviani A(2021)Software-like Compilation for Data Center FPGA AcceleratorsProceedings of the 11th International Symposium on Highly Efficient Accelerators and Reconfigurable Technologies10.1145/3468044.3468047(1-6)Online publication date: 21-Jun-2021
https://dl.acm.org/doi/10.1145/3468044.3468047
Bolchini CSandionigi C(2014)Design of Hardened Embedded Systems on Multi-FPGA PlatformsACM Transactions on Design Automation of Electronic Systems10.1145/267655120:1(1-26)Online publication date: 18-Nov-2014
https://dl.acm.org/doi/10.1145/2676551
Iturbe XBenkrid KArslan TAzkarate MMartinez I(2011)A (fault-tolerant)2 scheduler for real-time HW tasksProceedings of the 7th international conference on Reconfigurable computing: architectures, tools and applications10.5555/1987535.1987548(79-87)Online publication date: 23-Mar-2011
https://dl.acm.org/doi/10.5555/1987535.1987548
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Using Relocatable Bitstreams for Fault Tolerance
1. Hardware

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AHS '07: Proceedings of the Second NASA/ESA Conference on Adaptive Hardware and Systems

August 2007

736 pages

ISBN:076952866X

Publisher

IEEE Computer Society

United States

Publication History

Published: 05 August 2007

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Thomas JLavin CKaviani A(2021)Software-like Compilation for Data Center FPGA AcceleratorsProceedings of the 11th International Symposium on Highly Efficient Accelerators and Reconfigurable Technologies10.1145/3468044.3468047(1-6)Online publication date: 21-Jun-2021
https://dl.acm.org/doi/10.1145/3468044.3468047
Bolchini CSandionigi C(2014)Design of Hardened Embedded Systems on Multi-FPGA PlatformsACM Transactions on Design Automation of Electronic Systems10.1145/267655120:1(1-26)Online publication date: 18-Nov-2014
https://dl.acm.org/doi/10.1145/2676551
Iturbe XBenkrid KArslan TAzkarate MMartinez I(2011)A (fault-tolerant)2 scheduler for real-time HW tasksProceedings of the 7th international conference on Reconfigurable computing: architectures, tools and applications10.5555/1987535.1987548(79-87)Online publication date: 23-Mar-2011
https://dl.acm.org/doi/10.5555/1987535.1987548
Flynn AGordon-Ross AGeorge ABenini LDe Micheli GAl-Hashimi BMueller W(2009)Bitstream relocation with local clock domains for partially reconfigurable FPGAsProceedings of the Conference on Design, Automation and Test in Europe10.5555/1874620.1874691(300-303)Online publication date: 20-Apr-2009
https://dl.acm.org/doi/10.5555/1874620.1874691

Abstract

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Reconfigurable Fault Tolerance: A Comprehensive Framework for Reliable and Adaptive FPGA-Based Space Computing

Aging Resilience and Fault Tolerance in Runtime Reconfigurable Architectures

Low-Overhead Fault-Tolerance Technique for a Dynamically Reconfigurable Softcore Processor

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