Synthesis of pipelined DSP accelerators with dynamic scheduling

In this paper we present the design of an ASIC chip for real-time image processing in industrial applications. The chip is a module of a system for the automatic surface inspection of mechanical parts: it implements the feed-forward phase of a neural ...

To construct complete systems on silicon, application specific DSP accelerators are needed to speed up the execution of high throughput DSP algorithms. In this paper, a methodology is presented to synthesize high throughput DSP functions into ...

In this paper, we present a module generator which can produce variety of multiplier designs for LUT based FPGAs. It incorporates algorithms for generating sequential, combinational and pipelined designs. The multiplier generator forms a part of the ...