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Performance Evaluation of Congestion-Aware Routing with DVFS on a Millimeter-Wave Small-World Wireless NoC

Published: 18 November 2014 Publication History

Abstract

The mm-wave small-world wireless NoC (mSWNoC) has emerged as an enabling interconnection infrastructure for designing high-bandwidth and energy-efficient multicore chips. In this mSWNoC architecture, long-range communication predominately takes place through the wireless shortcuts operating in the range of 10--100GHz, whereas short-range data exchange occurs through conventional metal wires. This results in performance advantages (lower latency and energy dissipation), mainly stemming from using the wireless links as long-range shortcuts between far-apart cores. The performance gain introduced by the wireless channels can be enhanced further if the wireline links of the mSWNoC are optimized according to the traffic patterns arising out of the application workloads. While there is significant energy savings, and hence temperature reduction, in the network due to the mSWNoC architecture, a load-imbalanced network is still susceptible to local temperature hotspots. In this work, we demonstrate that by incorporating congestion-avoidance routing with network-level dynamic voltage and frequency scaling (DVFS) in an mSWNoC, the power and thermal profiles can be improved without a significant impact on the overall network performance. In this work, we demonstrate how novel interconnect architectures enabled by the on-chip wireless links coupled with power management strategies can improve the energy and thermal characteristics of an mSWNoC significantly without introducing any performance degradation with respect to the conventional mesh-based NoC.

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    cover image ACM Journal on Emerging Technologies in Computing Systems
    ACM Journal on Emerging Technologies in Computing Systems  Volume 11, Issue 2
    Special Issue on Reversible Computation and Regular Papers
    November 2014
    199 pages
    ISSN:1550-4832
    EISSN:1550-4840
    DOI:10.1145/2686762
    Issue’s Table of Contents
    Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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    Publication History

    Published: 18 November 2014
    Accepted: 01 July 2014
    Revised: 01 May 2014
    Received: 01 March 2014
    Published in JETC Volume 11, Issue 2

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    Author Tags

    1. DTM
    2. DVFS
    3. Multi-core
    4. NoC
    5. small world
    6. wireless links

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    • (2022)Design of a novel congestion-aware communication mechanism for wireless NoC in multicore systemsSignal and Data Processing10.52547/jsdp.19.1.4319:1(43-58)Online publication date: 1-May-2022
    • (2020)Exploiting Data Resilience in Wireless Network-on-chip ArchitecturesACM Journal on Emerging Technologies in Computing Systems10.1145/337944816:2(1-27)Online publication date: 4-Apr-2020
    • (2020)Implementing On-Chip Wireless Communication in Multi-stage Interconnection NoCsAdvanced Information Networking and Applications10.1007/978-3-030-44041-1_48(533-546)Online publication date: 28-Mar-2020
    • (2018)A General, Fault tolerant, Adaptive, Deadlock-free Routing Protocol for Network-on-chip2018 11th International Workshop on Network on Chip Architectures (NoCArc)10.1109/NOCARC.2018.8541212(1-6)Online publication date: Oct-2018
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    • (2016)Power and thermal management in massive multicore chipsProceedings of the International Conference on Compilers, Architectures and Synthesis for Embedded Systems10.1145/2968455.2974013(1-2)Online publication date: 1-Oct-2016
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