research-article

Performance Evaluation and Design Trade-Offs for Network-on-Chip Interconnect Architectures

Authors:

Partha Pratim Pande,

Cristian Grecu,

Resve SalehAuthors Info & Claims

IEEE Transactions on Computers, Volume 54, Issue 8

Pages 1025 - 1040

https://doi.org/10.1109/TC.2005.134

Published: 01 August 2005 Publication History

Abstract

Multiprocessor system-on-chip (MP-SoC) platforms are emerging as an important trend for SoC design. Power and wire design constraints are forcing the adoption of new design methodologies for system-on-chip (SoC), namely, those that incorporate modularity and explicit parallelism. To enable these MP-SoC platforms, researchers have recently pursued scaleable communication-centric interconnect fabrics, such as networks-on-chip (NoC), which possess many features that are particularly attractive for these. These communication-centric interconnect fabrics are characterized by different trade-offs with regard to latency, throughput, energy dissipation, and silicon area requirements. In this paper, we develop a consistent and meaningful evaluation methodology to compare the performance and characteristics of a variety of NoC architectures. We also explore design trade-offs that characterize the NoC approach and obtain comparative results for a number of common NoC topologies. To the best of our knowledge, this is the first effort in characterizing different NoC architectures with respect to their performance and design trade-offs. To further illustrate our evaluation methodology, we map a typical multiprocessing platform to different NoC interconnect architectures and show how the system performance is affected by these design trade-offs.

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Performance Evaluation and Design Trade-Offs for Network-on-Chip Interconnect Architectures

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Published In

cover image IEEE Transactions on Computers

IEEE Transactions on Computers Volume 54, Issue 8

August 2005

112 pages

ISSN:0018-9340

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Copyright © 2005.

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IEEE Computer Society

United States

Publication History

Published: 01 August 2005

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https://dl.acm.org/doi/10.1016/j.micpro.2024.105040
Patra RMaji PSrivastava DMondal H(2024)Machine learning-driven performance assessment of network-on-chip architecturesThe Journal of Supercomputing10.1007/s11227-024-06340-180:16(24483-24519)Online publication date: 1-Nov-2024
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https://dl.acm.org/doi/10.1145/3610396.3623266
Reza M(2023)Machine Learning Enabled Solutions for Design and Optimization Challenges in Networks-on-Chip based Multi/Many-Core ArchitecturesACM Journal on Emerging Technologies in Computing Systems10.1145/359147019:3(1-26)Online publication date: 30-Jun-2023
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Khamis MEl-Ashry SAbdElsalam MEl-Kharashi MShalaby A(2022)Emulation and verification framework for MPSoC based on NoC and RISC-VDesign Automation for Embedded Systems10.1007/s10617-022-09265-126:3-4(133-159)Online publication date: 14-Sep-2022
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