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Endurance-aware cache line management for non-volatile caches

Authors:

Norman P. JouppiAuthors Info & Claims

ACM Transactions on Architecture and Code Optimization (TACO), Volume 11, Issue 1

Article No.: 4, Pages 1 - 25

https://doi.org/10.1145/2579671

Published: 01 February 2014 Publication History

Abstract

Nonvolatile memories (NVMs) have the potential to replace low-level SRAM or eDRAM on-chip caches because NVMs save standby power and provide large cache capacity. However, limited write endurance is a common problem for NVM technologies, and today's cache management might result in unbalanced cache write traffic, causing heavily written cache blocks to fail much earlier than others. Although wear-leveling techniques for NVM-based main memories exist, we cannot simply apply them to NVM-based caches. This is because cache writes have intraset variations as well as interset variations, while writes to main memories only have interset variations.

To solve this problem, we propose i²WAP, a new cache management policy that can reduce both inter- and intraset write variations. i²WAP has two features: Swap-Shift, an enhancement based on existing main memory wear leveling to reduce cache interset write variations, and Probabilistic Set Line Flush, a novel technique to reduce cache intraset write variations. Implementing i²WAP only needs two global counters and two global registers. In one of our studies, i²WAP can improve the NVM cache lifetime by 75% on average and up to 224%. We also validate that i²WAP is effective in systems with different cache configurations and workloads.

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Cited By

Bagchi ADharamjeet Rishabh OSuri MPanda P(2024)POEM: Performance Optimization and Endurance Management for Non-volatile CachesACM Transactions on Design Automation of Electronic Systems10.1145/3653452Online publication date: 27-Mar-2024
https://doi.org/10.1145/3653452
Badri SSaini MGoel N(2023)Mapi-Pro: An Energy Efficient Memory Mapping Technique for Intermittent ComputingACM Transactions on Architecture and Code Optimization10.1145/3629524Online publication date: 20-Oct-2023
https://doi.org/10.1145/3629524
Gebregiorgis ADu Nguyen HYu JBishnoi RTaouil MCatthoor FHamdioui S(2022)A Survey on Memory-centric Computer ArchitecturesACM Journal on Emerging Technologies in Computing Systems10.1145/354497418:4(1-50)Online publication date: 25-Oct-2022
https://dl.acm.org/doi/10.1145/3544974
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Index Terms

Endurance-aware cache line management for non-volatile caches
1. Hardware
  1. Hardware test
    1. Memory test and repair

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Published In

cover image ACM Transactions on Architecture and Code Optimization

ACM Transactions on Architecture and Code Optimization Volume 11, Issue 1

February 2014

373 pages

ISSN:1544-3566

EISSN:1544-3973

DOI:10.1145/2591460

Issue’s Table of Contents

Copyright © 2014 ACM.

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Publication History

Published: 01 February 2014

Accepted: 01 October 2013

Revised: 01 July 2013

Received: 01 April 2013

Published in TACO Volume 11, Issue 1

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Cited By

Bagchi ADharamjeet Rishabh OSuri MPanda P(2024)POEM: Performance Optimization and Endurance Management for Non-volatile CachesACM Transactions on Design Automation of Electronic Systems10.1145/3653452Online publication date: 27-Mar-2024
https://doi.org/10.1145/3653452
Badri SSaini MGoel N(2023)Mapi-Pro: An Energy Efficient Memory Mapping Technique for Intermittent ComputingACM Transactions on Architecture and Code Optimization10.1145/3629524Online publication date: 20-Oct-2023
https://doi.org/10.1145/3629524
Gebregiorgis ADu Nguyen HYu JBishnoi RTaouil MCatthoor FHamdioui S(2022)A Survey on Memory-centric Computer ArchitecturesACM Journal on Emerging Technologies in Computing Systems10.1145/354497418:4(1-50)Online publication date: 25-Oct-2022
https://dl.acm.org/doi/10.1145/3544974
Shin DJang HOh KLee J(2022)An Energy-Efficient DRAM Cache Architecture for Mobile Platforms With PCM-Based Main MemoryACM Transactions on Embedded Computing Systems10.1145/345199521:1(1-22)Online publication date: 14-Jan-2022
https://dl.acm.org/doi/10.1145/3451995
Chen XYao LWang XSun ASheng Q(2022)Generative Adversarial Reward Learning for Generalized Behavior Tendency InferenceIEEE Transactions on Knowledge and Data Engineering10.1109/TKDE.2022.318692035:10(9878-9889)Online publication date: 3-Aug-2022
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Liu TWu QChang LGu T(2022)A review of deep learning-based recommender system in e-learning environmentsArtificial Intelligence Review10.1007/s10462-022-10135-255:8(5953-5980)Online publication date: 1-Dec-2022
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Nguyen HYu JLebdeh MTaouil MHamdioui SCatthoor F(2020)A Classification of Memory-Centric ComputingACM Journal on Emerging Technologies in Computing Systems10.1145/336583716:2(1-26)Online publication date: 30-Jan-2020
https://dl.acm.org/doi/10.1145/3365837
Bender MChowdhury RDas RJohnson RKuszmaul WLincoln ALiu QLynch JXu HScheideler CSpear M(2020)Closing the Gap Between Cache-oblivious and Cache-adaptive AnalysisProceedings of the 32nd ACM Symposium on Parallelism in Algorithms and Architectures10.1145/3350755.3400274(63-73)Online publication date: 6-Jul-2020
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Yu JLebdeh MNguyen HTaouil MHamdioui SCheng KYang H(2020)The Power of Computation-in-Memory Based on Memristive DevicesProceedings of the 25th Asia and South Pacific Design Automation Conference10.1109/ASP-DAC47756.2020.9045162(385-392)Online publication date: 17-Jan-2020
https://dl.acm.org/doi/10.1109/ASP-DAC47756.2020.9045162
Nguyen HYu JLebdeh MTaouil MHamdioui S(2019)A computation-in-memory accelerator based on resistive devicesProceedings of the International Symposium on Memory Systems10.1145/3357526.3357554(19-32)Online publication date: 30-Sep-2019
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