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Design and Evaluation of Technology-Agnostic Heterogeneous Networks-on-Chip

Published: 06 May 2014 Publication History

Abstract

Traditional metal-wire-based networks-on-chip (NoC) suffer from high latency and power dissipation as the system size scales up in the number of cores. This limitation stems from the inherent multihop communication nature of larger NoCs. It has previously been shown that the performance of NoCs can be significantly improved by introducing long-range, low power, and high-bandwidth single-hop links between distant cores. While previous work has focused on specific NoC architectures and configurations, it remains an open question whether heterogeneous link types are beneficial in a broad range of NoC architectures. In this article, we show that a generic NoC architecture with heterogeneous link types allows for NoCs with higher bandwidth at a lower cost compared to homogeneous networks. We further show that such NoCs scale up significantly better in terms of performance and cost. We demonstrate these broadly-applicable results by using a technology-agnostic complex network approach that targets NoC architectures with various emerging link types.

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Cited By

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  • (2020)A design flow for an optimized congestion-aware application-specific wireless network-on-chip architectureFuture Generation Computer Systems10.1016/j.future.2020.01.001106:C(234-249)Online publication date: 1-May-2020
  • (2016)A Novel Approach to Optimize Fault-Tolerant Hybrid Wireless Network-on-Chip ArchitecturesACM Journal on Emerging Technologies in Computing Systems10.1145/281457212:4(1-37)Online publication date: 15-Mar-2016
  • (2015)A study of a wire-wireless hybrid NoC architecture with an energy-proportional multicast scheme for energy efficiencyComputers and Electrical Engineering10.1016/j.compeleceng.2015.06.00545:C(402-416)Online publication date: 1-Jul-2015

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    cover image ACM Journal on Emerging Technologies in Computing Systems
    ACM Journal on Emerging Technologies in Computing Systems  Volume 10, Issue 3
    April 2014
    196 pages
    ISSN:1550-4832
    EISSN:1550-4840
    DOI:10.1145/2614448
    Issue’s Table of Contents
    Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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    Publication History

    Published: 06 May 2014
    Accepted: 01 March 2013
    Revised: 01 September 2012
    Received: 01 February 2012
    Published in JETC Volume 10, Issue 3

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    Author Tags

    1. Networks-on-chip
    2. heterogeneous
    3. optical
    4. wireless

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    View all
    • (2020)A design flow for an optimized congestion-aware application-specific wireless network-on-chip architectureFuture Generation Computer Systems10.1016/j.future.2020.01.001106:C(234-249)Online publication date: 1-May-2020
    • (2016)A Novel Approach to Optimize Fault-Tolerant Hybrid Wireless Network-on-Chip ArchitecturesACM Journal on Emerging Technologies in Computing Systems10.1145/281457212:4(1-37)Online publication date: 15-Mar-2016
    • (2015)A study of a wire-wireless hybrid NoC architecture with an energy-proportional multicast scheme for energy efficiencyComputers and Electrical Engineering10.1016/j.compeleceng.2015.06.00545:C(402-416)Online publication date: 1-Jul-2015

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