Co-simulation framework of SystemC SoC virtual prototype and custom logic (abstract only)

To address the increasing demand of System-on-Chip (SoC) for high performance applications and IP programmability, specialized SoC with custom logic is developed in a single chip or multi-chip system. Like any other SoC platforms, early software development before hardware availability using a Virtual Prototype (VP) is essential. However, the existing RTL for custom logic makes it non-trivial to simulate the entire system with software models written in high-level language (i.e. SystemC/C/C++). In this paper, we describe our unique virtual prototyping framework called "FPGA-In-the-Loop (FIL)" to enable co-simulation of software models in the VP and custom logic running in the FPGA at native speed. This platform enables designers to start early software development and integration of the entire hardware platform without needing to develop software models for custom logic. More importantly, our contributions lie in overcoming two of the biggest challenges in such co-simulation systems; 1) the communication channel performance bottleneck and 2) software-visible asynchronous signal timing correctness (i.e. interrupt). Our framework was able to 1) optimize communications between the VP and FPGA to achieve up to 872 Mbps effective throughput and 2) guarantee software-visible asynchronous signal delivery timing (i.e. interrupts) between the two simulation domains. Finally, we implemented our framework on a commercial hybrid platform with SoC and FPGA to demonstrate the complete embedded Linux stack communicating with custom video/touchscreen IPs running in the FPGA.