Article

An FPGA-based Pentium® in a complete desktop system

Authors:

Shih-Lien L. Lu,

Peter Yiannacouras,

Taeweon SuhAuthors Info & Claims

FPGA '07: Proceedings of the 2007 ACM/SIGDA 15th international symposium on Field programmable gate arrays

Pages 53 - 59

https://doi.org/10.1145/1216919.1216927

Published: 18 February 2007 Publication History

Abstract

Software simulation has been the predominant method for architects to evaluate microprocessor research proposals. There are three tenets in modeling new designs with software models: simulation speed, model accuracy and model completeness. The increasing complexity of the processor and accelerated trend to have multiple processors on a chip are putting burden on simulators to achieve all tenets mentioned, including accurately capturing OS effects. In this work we perform preliminary experimentation/prototyping with an emulation system which overcomes the tension to satisfy all three requirements. The system is an original Socket-7 based desktop processor system with typical hardware peripherals running modern operating systems such as Fedora Core 4 and Windows XP; however we have inserted a Xilinx Virtex-4 in place of the processor that should sit in the motherboard and have used the Virtex-4 to host a complete version of the Pentium® microprocessor (which consumes less than half its resources). We can therefore apply architectural changes to the processor and evaluate their effects on the complete desktop system. We use this FPGA-based emulation system to conduct preliminary architectural experiments including growing the branch target buffer and the level 1 caches. In addition, we experimented with interfacing hardware accelerators such as DES and AES engines which resulted in 27x speedups.

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Cited By

Lan MHuang LYang LMa SYan RWang YXu W(2022)Late-Stage Optimization of Modern ILP Processor Cores via FPGA SimulationApplied Sciences10.3390/app12231222512:23(12225)Online publication date: 29-Nov-2022
https://doi.org/10.3390/app122312225
Wong HBetz VRose J(2016)Microarchitecture and Circuits for a 200 MHz Out-of-Order Soft Processor Memory SystemACM Transactions on Reconfigurable Technology and Systems10.1145/297402210:1(1-22)Online publication date: 9-Dec-2016
https://dl.acm.org/doi/10.1145/2974022
Ogawa EMatsuda YMisono TKobayashi RKise K(2015)Reconfigurable IBM PC Compatible SoC for Computer Architecture Education and ResearchProceedings of the 2015 IEEE 9th International Symposium on Embedded Multicore/Many-core Systems-on-Chip10.1109/MCSoC.2015.35(65-72)Online publication date: 23-Sep-2015
https://dl.acm.org/doi/10.1109/MCSoC.2015.35
Show More Cited By

Index Terms

An FPGA-based Pentium® in a complete desktop system
1. Computer systems organization
  1. Architectures
    1. Other architectures
      1. Reconfigurable computing
      2. Self-organizing autonomic computing

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Published In

cover image ACM Conferences

FPGA '07: Proceedings of the 2007 ACM/SIGDA 15th international symposium on Field programmable gate arrays

February 2007

248 pages

ISBN:9781595936004

DOI:10.1145/1216919

General Chair:
André DeHon
University of Pennsylvania, USA
,
Program Chair:
Mike Hutton
Altera, USA

Copyright © 2007 ACM.

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Publication History

Published: 18 February 2007

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FPGA07

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FPGA07: ACM/SIGDA International Symposium on Field Programmable Gate Arrays 2007

February 18 - 20, 2007

California, Monterey, USA

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Overall Acceptance Rate 125 of 627 submissions, 20%

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Cited By

Lan MHuang LYang LMa SYan RWang YXu W(2022)Late-Stage Optimization of Modern ILP Processor Cores via FPGA SimulationApplied Sciences10.3390/app12231222512:23(12225)Online publication date: 29-Nov-2022
https://doi.org/10.3390/app122312225
Wong HBetz VRose J(2016)Microarchitecture and Circuits for a 200 MHz Out-of-Order Soft Processor Memory SystemACM Transactions on Reconfigurable Technology and Systems10.1145/297402210:1(1-22)Online publication date: 9-Dec-2016
https://dl.acm.org/doi/10.1145/2974022
Ogawa EMatsuda YMisono TKobayashi RKise K(2015)Reconfigurable IBM PC Compatible SoC for Computer Architecture Education and ResearchProceedings of the 2015 IEEE 9th International Symposium on Embedded Multicore/Many-core Systems-on-Chip10.1109/MCSoC.2015.35(65-72)Online publication date: 23-Sep-2015
https://dl.acm.org/doi/10.1109/MCSoC.2015.35
Libo Huang Yongwen Wang Qiang Dou Chengyi Zhang Caixia Sun Chao Xu (2015)Fast FPGA system for microarchitecture optimization on synthesizable modern processor design2015 25th International Conference on Field Programmable Logic and Applications (FPL)10.1109/FPL.2015.7294005(1-4)Online publication date: Sep-2015
https://doi.org/10.1109/FPL.2015.7294005
Huang YChen LCui ZRuan YBao YChen MSun N(2014)HMTTACM Transactions on Architecture and Code Optimization10.1145/257966811:1(1-25)Online publication date: 1-Feb-2014
https://dl.acm.org/doi/10.1145/2579668
Wong HBetz VRose J(2014)Quantifying the Gap Between FPGA and Custom CMOS to Aid Microarchitectural DesignIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2013.228428122:10(2067-2080)Online publication date: Oct-2014
https://doi.org/10.1109/TVLSI.2013.2284281
Ni NPeng YHutchings BBetz V(2013)Co-simulation framework of SystemC SoC virtual prototype and custom logic (abstract only)Proceedings of the ACM/SIGDA international symposium on Field programmable gate arrays10.1145/2435264.2435346(278-278)Online publication date: 11-Feb-2013
https://dl.acm.org/doi/10.1145/2435264.2435346
Dwiel BChoudhary NRotenberg E(2012)FPGA modeling of diverse superscalar processorsProceedings of the 2012 IEEE International Symposium on Performance Analysis of Systems & Software10.1109/ISPASS.2012.6189225(188-199)Online publication date: 1-Apr-2012
https://dl.acm.org/doi/10.1109/ISPASS.2012.6189225
Patil NBansal AChiou DStok LDutt NHassoun S(2011)Enforcing architectural contracts in high-level synthesisProceedings of the 48th Design Automation Conference10.1145/2024724.2024909(824-829)Online publication date: 5-Jun-2011
https://dl.acm.org/doi/10.1145/2024724.2024909
Wong HBetz VRose JWawrzynek JCompton K(2011)Comparing FPGA vs. custom cmos and the impact on processor microarchitectureProceedings of the 19th ACM/SIGDA international symposium on Field programmable gate arrays10.1145/1950413.1950419(5-14)Online publication date: 27-Feb-2011
https://dl.acm.org/doi/10.1145/1950413.1950419
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