research-article

Daedalus: toward composable multimedia MP-SoC design

Authors:

E. DeprettereAuthors Info & Claims

DAC '08: Proceedings of the 45th annual Design Automation Conference

Pages 574 - 579

https://doi.org/10.1145/1391469.1391615

Published: 08 June 2008 Publication History

Abstract

Daedalus is a system-level design flow for the design of multiprocessor system-on-chip (MP-SoC) based embedded multimedia systems. It offers a fully integrated tool-flow in which design space exploration (DSE), system-level synthesis, application mapping, and system prototyping of MP-SoCs are highly automated. In this paper, we describe our first industrial deployment experiences with the Daedalus framework. Daedalus is currently being deployed in the early stages of the design of an image compression system for very high resolution cameras targeting medical appliances. In this context, we performed a DSE study with a JPEG encoder application, which exploits both task and data parallelism. This application was mapped onto a range of different MP-SoC architectures. We achieved a performance speed-up of up to 20x compared to a single processor system. In addition, the results show that the Daedalus high-level MP-SoC models accurately predict the overall system performance, i.e., the performance error is around 5%.

References

[1]

Daedalus system-level design, http://daedalus.liacs.nl/.

[2]

D. Lyonnard et al. Automatic Generation of Application-Specific Architectures for Heterogeneous Multiprocessor System-on-Chip. In Proc. of the Design Automation Conference (DAC '2001), June 18--22 2001.

Digital Library

[3]

C. Erbas, A. D. Pimentel, M. Thompson, and S. Polstra. A framework for system-level modeling and simulation of embedded systems architectures. EURASIP Journal on Embedded Systems, vol. 2007, Article ID 82123, 2007.

Digital Library

[4]

A. Gerstlauer and D. Gajski. System-level abstraction semantics. In Proc. 15th Int. Symposium on System Synthesis (ISSS '02), pages 231--236, Oct. 2--4 2002.

Digital Library

[5]

C. Haubelt, J. Falk, J. Keinert, T. Schlichter, M. Streubuhr, A. Deyhle, A. Hadert, and J. Teich. A SystemC-Based Design Methodology for Digital Signal Processing Systems. EURASIP Journal on Embedded Systems, 2007:Article ID 47580, 22 pages, 2007.

Digital Library

[6]

K. Keutzer et al. System level design: Orthogonalization of concerns and platform-based design. IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, 19(12), Dec. 2000.

Digital Library

[7]

G. Kahn. The semantics of a simple language for parallel programming. In Proc. of the IFIP Congress 74, 1974.

[8]

M. J. Rutten et al. A Heterogeneous Multiprocessor Architecture for Flexible Media Processing. IEEE Design & Test of Computers, 19(4), 2002.

Digital Library

[9]

G. Martin. Overview of the MPSoC Design Challenge. In Proc. Design Automation Conference (DAC), San Francisco, USA, July 24--28 2006.

Digital Library

[10]

A. Mihal and K. Keutzer. Mapping concurrent applications onto architectural platforms. In A. Jantsch and H. Tenhunen, editors, Networks on Chips, pages 39--59. Kluwer Academic Publishers, 2003.

Digital Library

[11]

H. Nikolov, T. Stefanov, and E. F. Deprettere. Multi-processor system design with ESPAM. In Proc. of the Int. Conf. on HW/SW Codesign and System Synthesis (CODES+ISSS '06), pages 211--216, Oct. 2006.

Digital Library

[12]

H. Nikolov, T. Stefanov, and E. F. Deprettere. Systematic and automated multi-processor system design, programming, and implementation. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), 27(3):542--555, March 2008.

Digital Library

[13]

A. D. Pimentel, C. Erbas, and S. Polstra. A systematic approach to exploring embedded system architectures at multiple abstraction levels. IEEE Transactions on Computers, 55(2):99--112, 2006.

Digital Library

[14]

A. D. Pimentel, M. Thompson, S. Polstra, and C. Erbas. Calibration of abstract performance models for system-level design space exploration. Journal of Signal Processing Systems for Signal, Image, and Video Technology, 50(2), 2008.

Digital Library

[15]

T. Kangas et al. UML-based multi-processor SoC design framework. ACM Trans. on Embedded Computing Systems, 5(2):281--320, May 2006.

Digital Library

[16]

T. Stefanov et al. System design using Kahn process networks: The Compaan/Laura approach. In Proc. of the Int. Conference on Design, Automation and Test in Europe (DATE), pages 340--345, Feb. 2004.

Digital Library

[17]

M. Thompson, T. Stefanov, H. Nikolov, A. D. Pimentel, C. Erbas, S. Polstra, and E. F. Deprettere. A framework for rapid system-level exploration, synthesis, and programming of multimedia MP-SoCs. In Proc. of the Int. Conference on Hardware-Software Codesign and System Synthesis (CODES+ISSS '07), pages 9--14, 2007.

Digital Library

[18]

S. Verdoolaege, H. Nikolov, and T. Stefanov. PN: a tool for improved derivation of process networks. EURASIP Journal on Embedded Systems, vol. 2007, Article ID 75947, 2007.

Digital Library

Cited By

Frid NSruk VJakobović D(2022)Design Space Exploration of Clustered Sparsely Connected MPSoC PlatformsSensors10.3390/s2220780322:20(7803)Online publication date: 14-Oct-2022
https://doi.org/10.3390/s22207803
Pimentel A(2022)Methodologies for Design Space ExplorationHandbook of Computer Architecture10.1007/978-981-15-6401-7_23-1(1-31)Online publication date: 27-Jan-2022
https://doi.org/10.1007/978-981-15-6401-7_23-1
Jeong EJeong DHa S(2021)Dataflow Model–based Software Synthesis Framework for Parallel and Distributed Embedded SystemsACM Transactions on Design Automation of Electronic Systems10.1145/344768026:5(1-38)Online publication date: 5-Jun-2021
https://dl.acm.org/doi/10.1145/3447680
Show More Cited By

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Daedalus: toward composable multimedia MP-SoC design

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cover image ACM Conferences

DAC '08: Proceedings of the 45th annual Design Automation Conference

June 2008

993 pages

ISBN:9781605581156

DOI:10.1145/1391469

General Chair:
Limor Fix
Intel Research Pittsburgh, Pittsburgh, PA

Copyright © 2008 ACM.

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Published: 08 June 2008

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DAC '08: The 45th Annual Design Automation Conference 2008

June 8 - 13, 2008

California, Anaheim

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Overall Acceptance Rate 1,770 of 5,499 submissions, 32%

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Cited By

Frid NSruk VJakobović D(2022)Design Space Exploration of Clustered Sparsely Connected MPSoC PlatformsSensors10.3390/s2220780322:20(7803)Online publication date: 14-Oct-2022
https://doi.org/10.3390/s22207803
Pimentel A(2022)Methodologies for Design Space ExplorationHandbook of Computer Architecture10.1007/978-981-15-6401-7_23-1(1-31)Online publication date: 27-Jan-2022
https://doi.org/10.1007/978-981-15-6401-7_23-1
Jeong EJeong DHa S(2021)Dataflow Model–based Software Synthesis Framework for Parallel and Distributed Embedded SystemsACM Transactions on Design Automation of Electronic Systems10.1145/344768026:5(1-38)Online publication date: 5-Jun-2021
https://dl.acm.org/doi/10.1145/3447680
Merchant FSisejkovic DReimann LYasotharan KGrass TLeupers R(2021)ANDROMEDA: An FPGA Based RISC-V MPSoC Exploration Framework2021 34th International Conference on VLSI Design and 2021 20th International Conference on Embedded Systems (VLSID)10.1109/VLSID51830.2021.00051(270-275)Online publication date: Feb-2021
https://doi.org/10.1109/VLSID51830.2021.00051
Marwedel PMarwedel P(2021)Application MappingEmbedded System Design10.1007/978-3-030-60910-8_6(295-348)Online publication date: 26-Jan-2021
https://doi.org/10.1007/978-3-030-60910-8_6
Goens AMenard CCastrillon J(2019)On Compact Mappings for Multicore SystemsEmbedded Computer Systems: Architectures, Modeling, and Simulation10.1007/978-3-030-27562-4_23(325-335)Online publication date: 8-Aug-2019
https://doi.org/10.1007/978-3-030-27562-4_23
Zimmermann AMaschotta RWichmann AHilbrich R(2018)Optimization of systems with nested design space2018 Annual IEEE International Systems Conference (SysCon)10.1109/SYSCON.2018.8369550(1-8)Online publication date: Apr-2018
https://doi.org/10.1109/SYSCON.2018.8369550
Ha SJeong E(2018)Embedded Software Design Methodology Based on Formal Models of ComputationPrinciples of Modeling10.1007/978-3-319-95246-8_18(306-325)Online publication date: 20-Jul-2018
https://doi.org/10.1007/978-3-319-95246-8_18
Leupers RAguilar MCastrillon JSheng W(2018)Software Compilation Techniques for Heterogeneous Embedded Multi-Core SystemsHandbook of Signal Processing Systems10.1007/978-3-319-91734-4_28(1021-1062)Online publication date: 14-Oct-2018
https://doi.org/10.1007/978-3-319-91734-4_28
Hempel GGoens ACastrillon JAsmus JSbalzarini I(2017)Robust Mapping of Process Networks to Many-Core Systems using Bio-Inspired Design CenteringProceedings of the 20th International Workshop on Software and Compilers for Embedded Systems10.1145/3078659.3078667(21-30)Online publication date: 12-Jun-2017
https://dl.acm.org/doi/10.1145/3078659.3078667
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