Article

Automatic generation of application-specific architectures for heterogeneous multiprocessor system-on-chip

Authors:

Damien Lyonnard,

Ahmed A. JerrayaAuthors Info & Claims

DAC '01: Proceedings of the 38th annual Design Automation Conference

Pages 518 - 523

https://doi.org/10.1145/378239.379015

Published: 22 June 2001 Publication History

Abstract

We present a design flow for the generation of application-specific multiprocessor architectures. In the flow, architectural parameters are first extracted from a high-level system specification. Parameters are used to instantiate architectural components, such as processors, memory modules and communication networks. The flow includes the automatic generation of communication coprocessor that adapts the processor to the communication network in an application-specific way. Experiments with two system examples show the effectiveness of the presented design flow.

References

[1]

B. Ackland et al. A Single-Chip 1.6 Billion 16-b MAC/s Multiprocessor DSP. Custom Integrated Circuits Conference, 1999.

[2]

A. Baghdadi, D. Lyonnard, N. Zergainoh, and A. Jerraya. An efficient architecture model for systematic design of applicationspecific multiprocessor soc. Proc. Design Automation and Test in Europe, pages 55-62, Mar. 2001.

Digital Library

[3]

R. A. Bergamaschi and W. R. Lee. Designing Systems-on-Chip Using Cores. Proc. Design Automation Conf., June 2000.

Digital Library

[4]

Coware, Inc. N2C. available at http://www.coware.com/coware N2C.html.

[5]

D. Culler, J. P. Singh, and A. Gupta. Parallel Computer Architecture: A Hardware/Software Approach. Morgan Kaufmann Publishers, Aug. 1998.

Digital Library

[6]

D.D.Gajski,J.Zhu,R.D . o mer, A. Gerstlauer, and S. Zhao. SpecC: Specification Language and Methodology. Kluwer Academic Publishers., 2000.

[7]

L. Gauthier, S. Yoo, and A. Jerraya. Automatic generation and targeting of application specific operating systems and embedded system software. Proc. Design Automation and Test in Europe, pages 679- 685, Mar. 2001.

Digital Library

[8]

T. Gleerup et al. Memory Architecture for Efficient Utilization of SDRAM: A Case Study of the Computation/Memory Access Trade Off. Proc. Int'l Workshop on Hardware-Software Codesign,pages 51-55, May 2000.

Digital Library

[9]

P. Guerrier and A. Greiner. A Generic Architecture for On-Chip Packet-Switched Interconnections. Proc. Design Automation and Test in Europe, 2000.

Digital Library

[10]

F. Harmsze, A. Timmer, and J. van Meerbergen. Memory Arbitration nd Cache Management in Stream-Based Systems. Proc. Design Automation and Test in Europe, Mar. 2000.

Digital Library

[11]

M. Homewood and M. McLaren. Meiko CS-2 Interconnect Elan- Elite Design. Proc. of Hot Interconnects, pages 2.1.1-4, Aug. 1993.

[12]

IBM. The CoreConnect TM Bus Architecture. avail-able at http://www.chips.ibm.com/ product/ coreconnect/ docs/ crcon wp.pdf, 1999.

[13]

IBM, Inc. 28.4G Packet Routing Switch. Networking Technology Datasheets, available at http://www.chips.ibm.com/ product/ coreconnect/ docs/ crcon wp.pdf.

[14]

J. Kuskin et al. The Stanford FLASH Multiprocessor. Proc. of the 21st Int'l Symposium on Computer Architecture, 1994.

Digital Library

[15]

K. Lahiri, A. Raghunathan, G. Lakshminarayana, and S. Dey. Communication Architecture Tuners: A Methodology for the Design of High-Performance Communication Architectures for System-on- Chips. Proc. Design Automation Conf., June 2000.

Digital Library

[16]

J. A. J. Leijten et al. PROPHID: A Heterogeneous Multi-Processor Architecture for Multimedia. Proc. Int'l Conference on Computer Design, 1997.

Digital Library

[17]

J. A. J. Leijten et al. Stream Communication between Real-Time Tasks in a High-Performance Multiprocessor. Proc. Design Automation and Test in Europe, 1998.

Digital Library

[18]

C. K. Lennard, P. Schaumont, G. de Jong, A. Haverinen, and P. Hardee. Standards for System-Level Design: Practical Reality or Solution in Search of a Question? Proc. Design Automation and Test in Europe, Mar. 2000.

Digital Library

[19]

H. Lin and W. Wolf. Co Design of Interleaved Memory Systems. Proc. Int'l Workshop on Hardware-Software Codesign, pages 46-50, May 2000.

Digital Library

[20]

R. Lysecky, F. Vahid, and T. Givargis. Experiments with the Peripheral Virtual Component Interface. Proc. Int'l Symposium on System Synthesis, Sept. 2000.

Digital Library

[21]

T. Mattson et al. An Overview of the Intel TFLOPS Supercomputer. Intel Technology Journal, 1st quarter 1998.

[22]

R. S. Nikhil, G. M. Papadopoulos, and Arvind. *T: A Multithreaded Massively Parallel Architecture. Proc. of the 19th Int'l Symposium on Computer Architecture, pages 156-167, May 1992.

Digital Library

[23]

Sonics, Inc. Sonics -Networks, Technical Overview. Networking Technology Datasheets, available at http://www.sonicsinc.com/Documents/Overview.pdf, June 2000.

[24]

Synopsys, Inc. SystemC, Version 2.0. available at http://www.systemc.org/.

[25]

TIA/EIA-95A. Mobile Station-Base Station Compatibility Standard for Dual-Mode Wideband Spread Spectrum Cellular Systems. 1995.

[26]

S. Vercauteren, B. Lin, and H. D. Man. Constructing Application- Specific Heterogeneous Embedded Architectures from Custom HW/SW Applications. Proc. Design Automation Conf., June 1996.

Digital Library

[27]

S. Yoo, J. Lee, J. Jung, K. Rha, Y. Cho, and K. Choi. Fast Prototyping of an IS-95 CDMA Cellular Phone: a Case Study. Proc. the 6th Conference of Asia Pacific Chip Design Languages, pages 61-66, Oct. 1999.

Cited By

Jun TJambek AHashim U(2016)Performance comparison for signal amplitude analysis algorithms in nano biosensor application2016 IEEE EMBS Conference on Biomedical Engineering and Sciences (IECBES)10.1109/IECBES.2016.7843454(260-265)Online publication date: Dec-2016
https://doi.org/10.1109/IECBES.2016.7843454
Miyoshi SSasaki TFukazawa YKondo T(2015)An Architectural Framework of Snoopy Interconnection for Heterogeneous Cache SystemsProceedings of the 2015 Third International Symposium on Computing and Networking (CANDAR)10.1109/CANDAR.2015.44(561-565)Online publication date: 8-Dec-2015
https://dl.acm.org/doi/10.1109/CANDAR.2015.44
Meier MBreddemann MSpinczyk O(2015)Interfacing the hardware API with a feature-based operating system familyJournal of Systems Architecture: the EUROMICRO Journal10.1016/j.sysarc.2015.07.01061:10(531-538)Online publication date: 1-Nov-2015
https://dl.acm.org/doi/10.1016/j.sysarc.2015.07.010
Show More Cited By

Index Terms

Automatic generation of application-specific architectures for heterogeneous multiprocessor system-on-chip

Recommendations

Application-Specific FPGA using heterogeneous logic blocks

This work presents a new automatic mechanism to explore the solution space between Field Programmable Gate Arrays (FPGAs) and Application-Specific Integrated Circuits (ASICs). This new solution is termed as an Application-Specific Inflexible FPGA (ASIF) ...
Application-Specific Mesh-based Heterogeneous FPGA Architectures
Application specific FPGA using heterogeneous logic blocks
ARC'10: Proceedings of the 6th international conference on Reconfigurable Computing: architectures, Tools and Applications

An Application Specific Inflexible FPGA (ASIF) [12] is an FPGA with reduced flexibility that can implement a set of application circuits which will operate at different times. Application circuits are efficiently placed and routed on an FPGA in such a ...

Comments

Please enable JavaScript to view thecomments powered by Disqus.

Information & Contributors

Information

Published In

cover image ACM Conferences

DAC '01: Proceedings of the 38th annual Design Automation Conference

June 2001

863 pages

ISBN:1581132972

DOI:10.1145/378239

Chairman:
Jan Rabaey
Univ. of California

Copyright © 2001 ACM.

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

Sponsors

EDAC: Electronic Design Automation Consortium
SIGDA: ACM Special Interest Group on Design Automation
IEEE-CAS: Circuits & Systems

Publisher

Association for Computing Machinery

New York, NY, United States

Publication History

Published: 22 June 2001

Permissions

Request permissions for this article.

Request Permissions

Check for updates

Qualifiers

Article

Conference

DAC01

Sponsor:

EDAC
SIGDA
IEEE-CAS

DAC01: 38th ACM/IEEE-CAS/ EDAC Design Automation Conference

Nevada, Las Vegas, USA

Acceptance Rates

Overall Acceptance Rate 1,770 of 5,499 submissions, 32%

Upcoming Conference

DAC '25

Sponsor:
sigda

62nd ACM/IEEE Design Automation Conference

June 22 - 26, 2025

San Francisco , CA , USA

Contributors

Other Metrics

View Article Metrics

Bibliometrics & Citations

Bibliometrics

Article Metrics

107
Total Citations
View Citations
41
Total Downloads

Downloads (Last 12 months)3
Downloads (Last 6 weeks)1

Reflects downloads up to 22 Nov 2024

Other Metrics

View Author Metrics

Citations

Cited By

Jun TJambek AHashim U(2016)Performance comparison for signal amplitude analysis algorithms in nano biosensor application2016 IEEE EMBS Conference on Biomedical Engineering and Sciences (IECBES)10.1109/IECBES.2016.7843454(260-265)Online publication date: Dec-2016
https://doi.org/10.1109/IECBES.2016.7843454
Miyoshi SSasaki TFukazawa YKondo T(2015)An Architectural Framework of Snoopy Interconnection for Heterogeneous Cache SystemsProceedings of the 2015 Third International Symposium on Computing and Networking (CANDAR)10.1109/CANDAR.2015.44(561-565)Online publication date: 8-Dec-2015
https://dl.acm.org/doi/10.1109/CANDAR.2015.44
Meier MBreddemann MSpinczyk O(2015)Interfacing the hardware API with a feature-based operating system familyJournal of Systems Architecture: the EUROMICRO Journal10.1016/j.sysarc.2015.07.01061:10(531-538)Online publication date: 1-Nov-2015
https://dl.acm.org/doi/10.1016/j.sysarc.2015.07.010
Meier MBreddemann MSpinczyk O(2014)Hardware APIsProceedings of the 27th International Conference on Architecture of Computing Systems ARCS 2014 - Volume 835010.1007/978-3-319-04891-8_10(111-122)Online publication date: 25-Feb-2014
https://dl.acm.org/doi/10.1007/978-3-319-04891-8_10
Robino FOberg J(2013)The HeartBeat model: A platform abstraction enabling fast prototyping of real-time applications on NoC-based MPSoC on FPGA2013 8th International Workshop on Reconfigurable and Communication-Centric Systems-on-Chip (ReCoSoC)10.1109/ReCoSoC.2013.6581536(1-8)Online publication date: Jul-2013
https://doi.org/10.1109/ReCoSoC.2013.6581536
Javaid HParameswaran SJavaid HParameswaran S(2013)Literature SurveyPipelined Multiprocessor System-on-Chip for Multimedia10.1007/978-3-319-01113-4_2(21-52)Online publication date: 26-Nov-2013
https://doi.org/10.1007/978-3-319-01113-4_2
Filho S(2012)Task model suitable for dynamic load balancing of real-time applications in NoC-based MPSoCsProceedings of the 2012 IEEE 30th International Conference on Computer Design (ICCD 2012)10.1109/ICCD.2012.6378616(49-54)Online publication date: 30-Sep-2012
https://dl.acm.org/doi/10.1109/ICCD.2012.6378616
Štuikys VDamaševičius RŠtuikys VDamaševičius R(2012)Applications of Meta-Programming MethodologyMeta-Programming and Model-Driven Meta-Program Development10.1007/978-1-4471-4126-6_16(291-316)Online publication date: 7-Jun-2012
https://doi.org/10.1007/978-1-4471-4126-6_16
Li J(2011)BibliographyReal-Time Embedded Systems10.1201/b10935-12(187-207)Online publication date: 7-Jun-2011
https://doi.org/10.1201/b10935-12
Attia BWissem CNoureddine AZitouni ATorki KTourki R(2011)A new pipelined network interface for Network on Chip with latency and jitter optimizationICM 2011 Proceeding10.1109/ICM.2011.6177348(1-6)Online publication date: Dec-2011
https://doi.org/10.1109/ICM.2011.6177348
Show More Cited By

View Options

Login options

Check if you have access through your login credentials or your institution to get full access on this article.

Full Access

Get this Publication

View options

PDF

View or Download as a PDF file.

eReader

View online with eReader.

Media

Figures

Other

Tables

View Table of Contents