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Robust delay-fault test generation and synthesis for testability under a standard scan design methodology

Authors:

Kwang-Ting Cheng,

Srinivas Devadas,

Kurt KeutzerAuthors Info & Claims

DAC '91: Proceedings of the 28th ACM/IEEE Design Automation Conference

Pages 80 - 86

https://doi.org/10.1145/127601.127632

Published: 01 June 1991 Publication History

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Cited By

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Ashouei MChatterjee ASingh A(2010)Post-manufacture tuning for nano-CMOS yield recovery using reconfigurable logicIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2009.201455918:4(675-679)Online publication date: 1-Apr-2010
https://dl.acm.org/doi/10.1109/TVLSI.2009.2014559
Iwagaki TOhtake SFujiwara H(2008)Broadside Transition Test Generation for Partial Scan Circuits through Stuck-at Test GenerationVLSI-SoC: Research Trends in VLSI and Systems on Chip10.1007/978-0-387-74909-9_17(301-316)Online publication date: 2008
https://doi.org/10.1007/978-0-387-74909-9_17
Ashouei MNisar MChatterjee ASingh ADiril A(2007)Probabilistic Self-Adaptation of Nanoscale CMOS CircuitsProceedings of the 20th International Conference on VLSI Design held jointly with 6th International Conference: Embedded Systems10.1109/VLSID.2007.130(711-716)Online publication date: 6-Jan-2007
https://dl.acm.org/doi/10.1109/VLSID.2007.130
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Index Terms

Robust delay-fault test generation and synthesis for testability under a standard scan design methodology
1. Hardware
  1. Hardware test
    1. Test-pattern generation and fault simulation
  2. Very large scale integration design

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Published In

DAC '91: Proceedings of the 28th ACM/IEEE Design Automation Conference

June 1991

783 pages

ISBN:0897913957

DOI:10.1145/127601

Chairman:
A. Richard Newton
Univ. of California, Berkeley

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Association for Computing Machinery

New York, NY, United States

Publication History

Published: 01 June 1991

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DAC91: The 28th ACM/IEEE Design Automation Conference

June 17 - 22, 1991

California, San Francisco, USA

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Overall Acceptance Rate 1,770 of 5,499 submissions, 32%

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Cited By

View all

Ashouei MChatterjee ASingh A(2010)Post-manufacture tuning for nano-CMOS yield recovery using reconfigurable logicIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2009.201455918:4(675-679)Online publication date: 1-Apr-2010
https://dl.acm.org/doi/10.1109/TVLSI.2009.2014559
Iwagaki TOhtake SFujiwara H(2008)Broadside Transition Test Generation for Partial Scan Circuits through Stuck-at Test GenerationVLSI-SoC: Research Trends in VLSI and Systems on Chip10.1007/978-0-387-74909-9_17(301-316)Online publication date: 2008
https://doi.org/10.1007/978-0-387-74909-9_17
Ashouei MNisar MChatterjee ASingh ADiril A(2007)Probabilistic Self-Adaptation of Nanoscale CMOS CircuitsProceedings of the 20th International Conference on VLSI Design held jointly with 6th International Conference: Embedded Systems10.1109/VLSID.2007.130(711-716)Online publication date: 6-Jan-2007
https://dl.acm.org/doi/10.1109/VLSID.2007.130
Iwagaki TOhtake SFujiwara H(2006)A New Test Generation Model for Broadside Transition Testing of Partial Scan Circuits2006 IFIP International Conference on Very Large Scale Integration10.1109/VLSISOC.2006.313252(308-313)Online publication date: Oct-2006
https://doi.org/10.1109/VLSISOC.2006.313252
Lin YLu FCheng K(2006)Pseudofunctional testingIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2005.85737925:8(1535-1546)Online publication date: 1-Nov-2006
https://dl.acm.org/doi/10.1109/TCAD.2005.857379
Bhatia SJha N(2006)Synthesis for parallel scanIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/43.48666815:2(228-243)Online publication date: 1-Nov-2006
https://dl.acm.org/doi/10.1109/43.486668
Fuchs KPabst MRossel T(2006)RESISTIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/43.33141113:12(1550-1562)Online publication date: 1-Nov-2006
https://dl.acm.org/doi/10.1109/43.331411
Lin YLu FYang KCheng KTang T(2005)Constraint extraction for pseudo-functional scan-based delay testingProceedings of the 2005 Asia and South Pacific Design Automation Conference10.1145/1120725.1120797(166-171)Online publication date: 18-Jan-2005
https://dl.acm.org/doi/10.1145/1120725.1120797
Lin YLu FCheng K(2005)Pseudo-Functional Scan-based BIST for Delay FaultProceedings of the 23rd IEEE Symposium on VLSI Test10.1109/VTS.2005.69(229-234)Online publication date: 1-May-2005
https://dl.acm.org/doi/10.1109/VTS.2005.69
Yung-Chieh Lin Feng Lu Kai Yang Kwang-Ting Cheng (2005)Constraint extraction for pseudo-functional scan-based delay testingProceedings of the ASP-DAC 2005. Asia and South Pacific Design Automation Conference, 2005.10.1109/ASPDAC.2005.1466151(166-171)Online publication date: 2005
https://doi.org/10.1109/ASPDAC.2005.1466151
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High-level test synthesis with hierarchical test generation for delay-fault testability

Chiba Scan Delay Fault Testing with Short Test Application Time

Delay-fault test generation and synthesis for testability under a standard scan design methodology