On the design of robust multiple fault testable CMOS combinational logic circuits
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It is known that circuit delays and timing skews in input changes influence choice of tests to
detect delay faults. Tests for stuck-open faults in CMOS logic circuits could also be
invalidated by circuit delays and timing skews in input changes. Tests that detect modeled
faults independent of the delays in the circuit under test are called robust tests. An integrated
approach to the design of combinational logic circuits in which all single stuck-open faults
and path delay faults are detectable by robust tests was presented by the authors earlier …
detect delay faults. Tests for stuck-open faults in CMOS logic circuits could also be
invalidated by circuit delays and timing skews in input changes. Tests that detect modeled
faults independent of the delays in the circuit under test are called robust tests. An integrated
approach to the design of combinational logic circuits in which all single stuck-open faults
and path delay faults are detectable by robust tests was presented by the authors earlier …
Abstract
It is known that circuit delays and timing skews in input changes influence choice of tests to detect delay faults. Tests for stuck-open faults in CMOS logic circuits could also be invalidated by circuit delays and timing skews in input changes. Tests that detect modeled faults independent of the delays in the circuit under test are called robust tests. An integrated approach to the design of combinational logic circuits in which all single stuck-open faults and path delay faults are detectable by robust tests was presented by the authors earlier. This paper considers design of CMOS combinational logic circuits in which all multiple stuck-at, stuck-open and all multiple path delay faults are robustly testable.
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