article

Mechanisms for bounding vulnerabilities of processor structures

Authors:

Niranjan Kumar Soundararajan,

Angshuman Parashar,

Anand SivasubramaniamAuthors Info & Claims

ACM SIGARCH Computer Architecture News, Volume 35, Issue 2

Pages 506 - 515

https://doi.org/10.1145/1273440.1250725

Published: 09 June 2007 Publication History

Abstract

Concern for the increasing susceptibility of processor structures to transient errors has led to several recent research efforts that propose architectural techniques to enhance reliability. However, real systems are typically required to satisfy hard reliability budgets, and barring expensive full-redundancy approaches, none of the proposed solutions treat any reliability budgets or bounds as hard constraints. Meeting vulnerability bounds requires monitoring vulnerabilities of processor structures and taking appropriate actions whenever these bounds are violated. This mandates treating reliability as a first-order microarchitecture design constraint, while optimizing performance as long as reliability requirements are satisfied. This paper makes three key contributions towards this goal: (i) we present a simple infrastructure to monitor and provide upper bounds on the vulnerabilities of key processor structures at cycle-level fidelity; (ii) we propose two distinct control mechanisms - throttling and selective redundancy - to proactively and/or reactively bound the vulnerabilities to any limit specified by the system designer; (iii) within this framework, we propose a novel adaptation of Out-of-Order Commit for vulnerability reduction, which automatically provides additional leverage for the control mechanisms to boost performance while remaining within the reliability budget.

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Cited By

Vijayan AKiamehr SEbrahimi MChakrabarty KTahoori M(2018)Online Soft-Error Vulnerability Estimation for Memory Arrays and Logic CoresIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2017.270655837:2(499-511)Online publication date: 1-Feb-2018
https://dl.acm.org/doi/10.1109/TCAD.2017.2706558
Naithani AEyerman SEeckhout L(2017)Reliability-Aware Scheduling on Heterogeneous Multicore Processors2017 IEEE International Symposium on High Performance Computer Architecture (HPCA)10.1109/HPCA.2017.12(397-408)Online publication date: Feb-2017
https://doi.org/10.1109/HPCA.2017.12
Mittal SVetter J(2016)A Survey of Techniques for Modeling and Improving Reliability of Computing SystemsIEEE Transactions on Parallel and Distributed Systems10.1109/TPDS.2015.242617927:4(1226-1238)Online publication date: 1-Apr-2016
https://dl.acm.org/doi/10.1109/TPDS.2015.2426179
Show More Cited By

Index Terms

Mechanisms for bounding vulnerabilities of processor structures
1. Computer systems organization
  1. Architectures

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Mechanisms for bounding vulnerabilities of processor structures
ISCA '07: Proceedings of the 34th annual international symposium on Computer architecture

Concern for the increasing susceptibility of processor structures to transient errors has led to several recent research efforts that propose architectural techniques to enhance reliability. However, real systems are typically required to satisfy hard ...
SlicK: slice-based locality exploitation for efficient redundant multithreading
ASPLOS XII: Proceedings of the 12th international conference on Architectural support for programming languages and operating systems

Transient faults are expected a be a major design consideration in future microprocessors. Recent proposals for transient fault detection in processor cores have revolved around the idea of redundant threading, which involves redundant execution of a ...
SlicK: slice-based locality exploitation for efficient redundant multithreading
Proceedings of the 2006 ASPLOS Conference

Transient faults are expected a be a major design consideration in future microprocessors. Recent proposals for transient fault detection in processor cores have revolved around the idea of redundant threading, which involves redundant execution of a ...

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Information & Contributors

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Published In

cover image ACM SIGARCH Computer Architecture News

ACM SIGARCH Computer Architecture News Volume 35, Issue 2

May 2007

527 pages

ISSN:0163-5964

DOI:10.1145/1273440

Issue’s Table of Contents

ISCA '07: Proceedings of the 34th annual international symposium on Computer architecture
June 2007
542 pages
ISBN:9781595937063
DOI:10.1145/1250662
General Chair:
Dean Tullsen
University of California, San Diego
,
Program Chair:
Brad Calder
Microsoft & University of California, San Diego

Copyright © 2007 ACM.

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Association for Computing Machinery

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Publication History

Published: 09 June 2007

Published in SIGARCH Volume 35, Issue 2

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Cited By

Vijayan AKiamehr SEbrahimi MChakrabarty KTahoori M(2018)Online Soft-Error Vulnerability Estimation for Memory Arrays and Logic CoresIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2017.270655837:2(499-511)Online publication date: 1-Feb-2018
https://dl.acm.org/doi/10.1109/TCAD.2017.2706558
Naithani AEyerman SEeckhout L(2017)Reliability-Aware Scheduling on Heterogeneous Multicore Processors2017 IEEE International Symposium on High Performance Computer Architecture (HPCA)10.1109/HPCA.2017.12(397-408)Online publication date: Feb-2017
https://doi.org/10.1109/HPCA.2017.12
Mittal SVetter J(2016)A Survey of Techniques for Modeling and Improving Reliability of Computing SystemsIEEE Transactions on Parallel and Distributed Systems10.1109/TPDS.2015.242617927:4(1226-1238)Online publication date: 1-Apr-2016
https://dl.acm.org/doi/10.1109/TPDS.2015.2426179
Tang LHuang Z(2016)A method for issue queue soft error vulnerability mitigation2016 17th IEEE/ACIS International Conference on Software Engineering, Artificial Intelligence, Networking and Parallel/Distributed Computing (SNPD)10.1109/SNPD.2016.7515938(443-450)Online publication date: May-2016
https://doi.org/10.1109/SNPD.2016.7515938
Duan LZhang YLi BPeng L(2014)Comprehensive and Efficient Design Parameter Selection for Soft Error Resilient Processors via Universal RulesIEEE Transactions on Computers10.1109/TC.2013.2463:9(2201-2214)Online publication date: Sep-2014
https://doi.org/10.1109/TC.2013.24
Yin YChen YGuo QChen T(2014)Prevention from Soft Errors via Architecture ElasticityJournal of Computer Science and Technology10.1007/s11390-014-1427-829:2(247-254)Online publication date: 23-Mar-2014
https://doi.org/10.1007/s11390-014-1427-8
Ma ACheng YXing Z(2011)Accurate and Simplified Prediction of AVF for Delay and Energy Efficient Cache DesignJournal of Computer Science and Technology10.1007/s11390-011-1150-726:3(504-519)Online publication date: 12-May-2011
https://doi.org/10.1007/s11390-011-1150-7
Naithani AEeckhout L(2022)Reliability-Aware Runahead2022 IEEE International Symposium on High-Performance Computer Architecture (HPCA)10.1109/HPCA53966.2022.00062(772-785)Online publication date: Apr-2022
https://doi.org/10.1109/HPCA53966.2022.00062
Sorin DSorin D(2022)IntroductionFault Tolerant Computer Architecture10.1007/978-3-031-01723-0_1(1-17)Online publication date: 5-Mar-2022
https://doi.org/10.1007/978-3-031-01723-0_1
Lim HKim TKang S(2020)Prediction-Based Error Correction for GPU Reliability with Low OverheadElectronics10.3390/electronics91118499:11(1849)Online publication date: 5-Nov-2020
https://doi.org/10.3390/electronics9111849
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