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Slipstream processors: improving both performance and fault tolerance

Authors:

Karthik Sundaramoorthy,

Eric RotenburgAuthors Info & Claims

ASPLOS IX: Proceedings of the ninth international conference on Architectural support for programming languages and operating systems

Pages 257 - 268

https://doi.org/10.1145/378993.379247

Published: 12 November 2000 Publication History

Abstract

Processors execute the full dynamic instruction stream to arrive at the final output of a program, yet there exist shorter instruction streams that produce the same overall effect. We propose creating a shorter but otherwise equivalent version of the original program by removing ineffectual computation and computation related to highly-predictable control flow. The shortened program is run concurrently with the full program on a chip multiprocessor simultaneous multithreaded processor, with two key advantages:1) Improved single-program performance. The shorter program speculatively runs ahead of the full program and supplies the full program with control and data flow outcomes. The full program executes efficiently due to the communicated outcomes, at the same time validating the speculative, shorter program. The two programs combined run faster than the original program alone. Detailed simulations of an example implementation show an average improvement of 7% for the SPEC95 integer benchmarks.2) Fault tolerance. The shorter program is a subset of the full program and this partial-redundancy is transparently leveraged for detecting and recovering from transient hardware faults.

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Index Terms

Slipstream processors: improving both performance and fault tolerance

Recommendations

Slipstream processors: improving both performance and fault tolerance
Special Issue: Proceedings of the ninth international conference on Architectural support for programming languages and operating systems (ASPLOS '00)

Processors execute the full dynamic instruction stream to arrive at the final output of a program, yet there exist shorter instruction streams that produce the same overall effect. We propose creating a shorter but otherwise equivalent version of the ...
Slipstream processors: improving both performance and fault tolerance

Processors execute the full dynamic instruction stream to arrive at the final output of a program, yet there exist shorter instruction streams that produce the same overall effect. We propose creating a shorter but otherwise equivalent version of the ...
Slipstream processors: improving both performance and fault tolerance

Processors execute the full dynamic instruction stream to arrive at the final output of a program, yet there exist shorter instruction streams that produce the same overall effect. We propose creating a shorter but otherwise equivalent version of the ...

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cover image ACM Conferences

ASPLOS IX: Proceedings of the ninth international conference on Architectural support for programming languages and operating systems

November 2000

271 pages

ISBN:1581133170

DOI:10.1145/378993

Chairmen:
Larry Rudolph
MIT, Cambridge, MA
,
Anoop Gupta
Microsoft

ACM SIGOPS Operating Systems Review Volume 34, Issue 5
Dec. 2000
269 pages
ISSN:0163-5980
DOI:10.1145/384264
Chairman:
William E. Weihl
Akami technologies, Inc., San Mateo, CA
Issue’s Table of Contents
ACM SIGARCH Computer Architecture News Volume 28, Issue 5
Special Issue: Proceedings of the ninth international conference on Architectural support for programming languages and operating systems (ASPLOS '00)
Dec. 2000
269 pages
ISSN:0163-5964
DOI:10.1145/378995
Editor:
Doug DeGroot
Dallas, TX
Issue’s Table of Contents

Copyright © 2000 ACM.

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Published: 12 November 2000

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ASPLOS IX Paper Acceptance Rate 24 of 114 submissions, 21%;

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Mehta S(2023)Speculative Register Reclamation2023 IEEE International Symposium on High-Performance Computer Architecture (HPCA)10.1109/HPCA56546.2023.10071122(1182-1194)Online publication date: Feb-2023
https://doi.org/10.1109/HPCA56546.2023.10071122
Khojasteh HTabatabaei H(2023)A Survey on the Proposed Architectures for Efficient Execution of Irregular Applications Using Pipeline Parallelism2023 Congress in Computer Science, Computer Engineering, & Applied Computing (CSCE)10.1109/CSCE60160.2023.00342(2080-2087)Online publication date: 24-Jul-2023
https://doi.org/10.1109/CSCE60160.2023.00342
Naithani AEeckhout L(2022)Reliability-Aware Runahead2022 IEEE International Symposium on High-Performance Computer Architecture (HPCA)10.1109/HPCA53966.2022.00062(772-785)Online publication date: Apr-2022
https://doi.org/10.1109/HPCA53966.2022.00062
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