Article

A fast block structure preserving model order reduction for inverse inductance circuits

Authors:

Hao Yu,

Yiyu Shi,

Lei He,

David SmartAuthors Info & Claims

ICCAD '06: Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design

Pages 7 - 12

https://doi.org/10.1145/1233501.1233504

Published: 05 November 2006 Publication History

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Abstract

Most existing RCL^-1 circuit reductions stamp inverse inductance L^-1 elements by a second-order nodal analysis (NA). The NA formulation uses nodal voltage variables and describes inductance by nodal susceptance. This leads to a singular matrix stamping in general. We introduce a new circuit stamping for RCL^-1 circuits using branch vector potentials. The new circuit stamping results in a first-order circuit matrix that is semi-positive definite and non-singular. We call this as vectorpotential based nodal analysis (VNA). It enables an accurate and passive reduction. In addition, to preserve the structure of state matrices such as sparsity and hierarchy, we represent the flat VNA matrix in a bordered-block diagonal (BBD) form. This enables us to build and simulate the macromodel efficiently. In experiments performed on several test cases, our method achieves up to 15X faster modeling building time, up to 33X faster simulation time, and as much as 67X smaller waveform error compared to SAPOR, the best existing second order RCL^-1 reduction method.

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Cited By

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Miettinen PHonkala MRoos JValtonen M(2011)PartMORIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2010.209075130:3(374-387)Online publication date: 1-Mar-2011
https://dl.acm.org/doi/10.1109/TCAD.2010.2090751
Miettinen PHonkala MRoos JValtonen M(2011)Improving Model-Order Reduction Methods by Singularity ExclusionScientific Computing in Electrical Engineering SCEE 201010.1007/978-3-642-22453-9_41(387-394)Online publication date: 24-Oct-2011
https://doi.org/10.1007/978-3-642-22453-9_41
Boyuan Yan Tan SMcGaughy B(2008)Second-Order Balanced Truncation for Passive-Order Reduction of RLCK CircuitsIEEE Transactions on Circuits and Systems II: Express Briefs10.1109/TCSII.2008.92565555:9(942-946)Online publication date: Sep-2008
https://doi.org/10.1109/TCSII.2008.925655
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Index Terms

A fast block structure preserving model order reduction for inverse inductance circuits
1. Hardware
  1. Electronic design automation
    1. Physical design (EDA)

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Published In

ICCAD '06: Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design

November 2006

147 pages

ISBN:1595933891

DOI:10.1145/1233501

General Chair:
Soha Hassoun
Tufts Univ., Medford, MA

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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New York, NY, United States

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Published: 05 November 2006

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IEEE-CS

ICCAD06: The International Conference on Computer-Aided Design 2006

November 5 - 9, 2006

California, San Jose

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Overall Acceptance Rate 457 of 1,762 submissions, 26%

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Miettinen PHonkala MRoos JValtonen M(2011)PartMORIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2010.209075130:3(374-387)Online publication date: 1-Mar-2011
https://dl.acm.org/doi/10.1109/TCAD.2010.2090751
Miettinen PHonkala MRoos JValtonen M(2011)Improving Model-Order Reduction Methods by Singularity ExclusionScientific Computing in Electrical Engineering SCEE 201010.1007/978-3-642-22453-9_41(387-394)Online publication date: 24-Oct-2011
https://doi.org/10.1007/978-3-642-22453-9_41
Boyuan Yan Tan SMcGaughy B(2008)Second-Order Balanced Truncation for Passive-Order Reduction of RLCK CircuitsIEEE Transactions on Circuits and Systems II: Express Briefs10.1109/TCSII.2008.92565555:9(942-946)Online publication date: Sep-2008
https://doi.org/10.1109/TCSII.2008.925655
Zhang LYu WZhu HZhang WCheng C(2008)Clock Skew Analysis via Vector Fitting in Frequency Domain9th International Symposium on Quality Electronic Design (isqed 2008)10.1109/ISQED.2008.4479780(476-479)Online publication date: Mar-2008
https://doi.org/10.1109/ISQED.2008.4479780
Yu HChu CHe LLevitan S(2007)Off-chip decoupling capacitor allocation for chip package co-designProceedings of the 44th annual Design Automation Conference10.1145/1278480.1278635(618-621)Online publication date: 4-Jun-2007
https://dl.acm.org/doi/10.1145/1278480.1278635

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Multiple block structure-preserving reduced order modeling of interconnect circuits

Updating incomplete factorization preconditioners for model order reduction

Wideband passive multiport model order reduction and realization of RLCM circuits

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