Abstract
This paper presents a framework for estimating the timing yield of sequential networks in the presence of process variations. We present an accurate method for characterizing various parameters such as setup time, hold time, clock to output delay etc. of sequential elements in the network. Using these models and the models of interconnects gate delays, and clock skews, we perform statistical timing analysis of combinational blocks in the circuit. The result of the timing analysis is a set of constraints involving random process variables that the network has to satisfy together in order to work correctly. We compute the joint yield of all the constraints to estimate the yield of the entire network. The proposed method provides a speedup of up to 400× compared to 10000 Monte Carlo simulations with an average error of less than 1% and 5% in mean and standard deviation respectively.
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References
Agarwal, A., Blaauw, D., Zolotov, V.: Statistical timing analysis for intra-die process variations with spatial correlations. In: Proc. of ICCAD (2003)
Bhardwaj, S., Ghanta, P., Vrudhula, S.: A framework for statistical timing analysis using non-linear delay and slew models. In: ICCAD 2006: Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design, New York, NY, USA, pp. 225–230. ACM Press, New York (2006)
Borkar, S., et al.: Parameteric variations and impact on circuits and microarchitecture. In: Proc. DAC (2003)
Chang, H., Sapatnekar, S.: Full-chip analysis of leakage power under process variations, including spatial correlations. In: IEEE/ACM Design Automation Conference, 2005, pp. 523–528. ACM Press, New York (2005)
Chang, H., Sapatnekar, S.S.: Statistical timing analysis under spatial correlations. IEEE Transactions on CAD (2005)
Chen, C.C.-P., Zhang, L., Hu, Y.: Statistical timing analysis in sequential circuit for on-chip global interconnect pipelining. In: IEEE DAC (2004)
Clark, C.E.: The greatest of a finite set of random variables. In: Operations Research (1961)
Ghanem, R.G., Spanos, P.: Stochastic Finite Elements: A Spectral Approach. Springer, Heidelberg (1991)
Jindrich, Z., Paul, F.: General framework for removal of clock network pessimism. In: IEEE/ACM ICCAD (2002)
Karnik, T., Borkar, S., De, V.: Sub-90 nm technologies-challenges and opportunities for cad. In: IEEE/ACM International Conference on CAD, 2002, ACM Press, New York (2002)
Keese, A., Matthies, H.G.: Numerical methods and smolyak quadrature for nonlinear stochastic partial differential equations. Technical report, Institute of Scientific Computing, Brunswick (2003)
Ling, W., Savaria, Y.: Analysis of wave-pipelined domino logic circuit and clocking styles subject to parametric variations. In: International Symposium on Quality Electronic Design (2006)
Mehrotra, V., Nassif, S., Boning, D., Chung, J.: Modeling the effects of manufacturing variation on high-speed microprocessor interconnect performance. In: International Electronic Devices Meeting, pp. 767–770. IEEE, Los Alamitos (December 1998)
Okada, K., Yamaoka, K., Onodera, H.: A statistical gate-delay model considering inra-gate variability. In: IEEE/ACM ICCAD (2003)
Pan, M., Chu, C.C.-N., Zhou, H.: Timing yield estimation using static timing analysis. In: IEEE International Symposium on Circuits and Systems (2005)
Rao, R., Devgan, A., Blaauw, D., Sylvester, D.: Parametric yield estimation considering leakage variability. In: Proc. of DAC (2004)
Roy, K., Mahmoodi, H., Mukhopadhyay, S.: Estimation of delay variations due to random-dopant fluctuations in nanoscale cmos circuits. IEEE Journal of Solid-State Circuits (2005)
Visweswariah, C., et al.: First-order incremental Block-Based Statistical Timing Analysis. In: IEEE/ACM Design Automation Conference, 2004, pp. 331–336 (2004)
Wang, J., Ghanta, P., Vrudhula, S.: Stochastic Analysis of Interconnect Performance in the Presence of Process Variations. In: Proc. of ICCAD (2004)
Zhan, Y., et al.: Correlation-aware statistical timing analysis with non-gaussian delay distributions. In: IEEE DAC, November 2005, IEEE Computer Society Press, Los Alamitos (2005)
Zhang, L., et al.: Correlation-Preserved Non-Gaussian Statistical Timing Analysis with Quadratic Timing Model. In: Proc. of DAC (2005)
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Goel, A., Bhardwaj, S., Ghanta, P., Vrudhula, S. (2007). Computation of Joint Timing Yield of Sequential Networks Considering Process Variations. In: Azémard, N., Svensson, L. (eds) Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation. PATMOS 2007. Lecture Notes in Computer Science, vol 4644. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-540-74442-9_13
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DOI: https://doi.org/10.1007/978-3-540-74442-9_13
Publisher Name: Springer, Berlin, Heidelberg
Print ISBN: 978-3-540-74441-2
Online ISBN: 978-3-540-74442-9
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