article

Equivalence checking between behavioral and RTL descriptions with virtual controllers and datapaths

Author:

Masahiro FujitaAuthors Info & Claims

ACM Transactions on Design Automation of Electronic Systems (TODAES), Volume 10, Issue 4

Pages 610 - 626

https://doi.org/10.1145/1109118.1109121

Published: 01 October 2005 Publication History

Abstract

In this article, we present techniques for comparison between behavioral level and register transfer level (RTL) design descriptions by mapping the designs into virtual controllers and virtual datapaths. We also discuss about how the equivalence between behavioral level and RTL designs can be defined precisely using the proposed “attribute statements” in an interactive fashion. Implementation issues as well as considerations on real life industrial design examples are also presented.

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Cited By

Abderehman MPatidar JOza JNigam YKhader TKarfa C(2022)FastSim: A Fast Simulation Framework for High-Level SynthesisIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2021.309033941:5(1371-1385)Online publication date: May-2022
https://doi.org/10.1109/TCAD.2021.3090339
Campbell KLin DHe LYang LGurumani SRupnow KMitra SChen D(2019)Hybrid Quick Error Detection: Validation and Debug of SoCs Through High-Level SynthesisIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2018.283710338:7(1345-1358)Online publication date: Jul-2019
https://doi.org/10.1109/TCAD.2018.2837103
Azarbad MAlizadeh B(2016)Scalable SMT-Based Equivalence Checking of Nested Loop Pipelining in Behavioral SynthesisACM Transactions on Design Automation of Electronic Systems10.1145/295387922:2(1-22)Online publication date: 26-Dec-2016
https://dl.acm.org/doi/10.1145/2953879
Show More Cited By

Index Terms

Equivalence checking between behavioral and RTL descriptions with virtual controllers and datapaths
1. Hardware
  1. Electronic design automation
    1. Hardware description languages and compilation
  2. Hardware validation
    1. Functional verification

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Information & Contributors

Information

Published In

cover image ACM Transactions on Design Automation of Electronic Systems

ACM Transactions on Design Automation of Electronic Systems Volume 10, Issue 4

October 2005

137 pages

ISSN:1084-4309

EISSN:1557-7309

DOI:10.1145/1109118

Issue’s Table of Contents

Copyright © 2005 ACM.

Publisher

Association for Computing Machinery

New York, NY, United States

Journal Family

ACM Journals for the Design of Smart and Connected Systems

Publication History

Published: 01 October 2005

Published in TODAES Volume 10, Issue 4

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Cited By

Abderehman MPatidar JOza JNigam YKhader TKarfa C(2022)FastSim: A Fast Simulation Framework for High-Level SynthesisIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2021.309033941:5(1371-1385)Online publication date: May-2022
https://doi.org/10.1109/TCAD.2021.3090339
Campbell KLin DHe LYang LGurumani SRupnow KMitra SChen D(2019)Hybrid Quick Error Detection: Validation and Debug of SoCs Through High-Level SynthesisIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2018.283710338:7(1345-1358)Online publication date: Jul-2019
https://doi.org/10.1109/TCAD.2018.2837103
Azarbad MAlizadeh B(2016)Scalable SMT-Based Equivalence Checking of Nested Loop Pipelining in Behavioral SynthesisACM Transactions on Design Automation of Electronic Systems10.1145/295387922:2(1-22)Online publication date: 26-Dec-2016
https://dl.acm.org/doi/10.1145/2953879
Carrion Schafer B(2016)Source Code Error Detection in High-Level Synthesis Functional VerificationIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2015.239703624:1(301-312)Online publication date: 1-Jan-2016
https://dl.acm.org/doi/10.1109/TVLSI.2015.2397036
Campbell KLin DMitra SChen D(2015)Hybrid quick error detection (H-QED)Proceedings of the 52nd Annual Design Automation Conference10.1145/2744769.2753768(1-6)Online publication date: 7-Jun-2015
https://dl.acm.org/doi/10.1145/2744769.2753768
Hu JLi TLi S(2015)Equivalence checking between SLM and TLM using coverage directed simulationFrontiers of Computer Science: Selected Publications from Chinese Universities10.1007/s11704-015-4257-09:6(934-943)Online publication date: 1-Dec-2015
https://dl.acm.org/doi/10.1007/s11704-015-4257-0
Bombieri NFummi FGuarnieri VPravadelli GStefanni FGhasempouri TLora MAuditore GMarcigaglia M(2015)Reusing RTL Assertion Checkers for Verification of SystemC TLM ModelsJournal of Electronic Testing: Theory and Applications10.1007/s10836-015-5514-831:2(167-180)Online publication date: 1-Apr-2015
https://dl.acm.org/doi/10.1007/s10836-015-5514-8
Bombieri NFummi FGuarnieri VPravadelli GStefanni FGhasempouri TLora MAuditore GMarcigaglia M(2014)On the reuse of RTL assertions in SystemC TLM verification2014 15th Latin American Test Workshop - LATW10.1109/LATW.2014.6841903(1-6)Online publication date: Mar-2014
https://doi.org/10.1109/LATW.2014.6841903
Hu JLi TLi S(2013)Equivalence Checking between SLM and TLM Using Coverage Directed SimulationProceedings of the 2013 International Conference on Computer-Aided Design and Computer Graphics10.1109/CADGraphics.2013.21(101-106)Online publication date: 16-Nov-2013
https://dl.acm.org/doi/10.1109/CADGraphics.2013.21
Karfa CMandal CSarkar D(2012)Formal verification of code motion techniques using data-flow-driven equivalence checkingACM Transactions on Design Automation of Electronic Systems10.1145/2209291.220930317:3(1-37)Online publication date: 5-Jul-2012
https://dl.acm.org/doi/10.1145/2209291.2209303
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